公开(公告)号：US20250139194A1

公开(公告)日：2025-05-01

申请号：US18823847

申请日：2024-09-04

Applicant: Samsung Electronics Co., Ltd. ,  NAVER CORPORATION

Inventor： Younho JEON ,  Hong Rak SON ,  Wonsuk SONG ,  Younggeon YOO ,  JongYoon YOON ,  Jihoon LIM ,  Jae Hun JANG ,  Sejung KWON ,  Byeoungwook KIM ,  Baeseong PARK ,  Dongsoo LEE

IPC: G06F17/16 ,  G06F5/01 ,  H03M7/24

Abstract: A matrix multiplier includes an input vector scaler configured to generate a first scaled input vector based on a first input vector and a plurality of quantization scale coefficients, a first data type converter configured to generate a first fixed-point scaled input vector based on the first scaled input vector, a processing element array including a first processing element configured to generate a first fixed-point output element based on the first fixed-point scaled input vector and first plurality of quantization sign values and a second processing element configured to generate a second fixed-point output element based on the first fixed-point scaled input vector and second plurality of quantization sign values, and a second data type converter configured to generate first and second output elements by converting data type of the first and second fixed-point output elements, and to output a first output vector including the first and second output elements.

公开(公告)号：US20250117257A1

公开(公告)日：2025-04-10

申请号：US18830998

申请日：2024-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungmin AHN ,  Hong Rak SON ,  Dong-Min SHIN ,  Dae-Yeol YANG ,  JongYoon YOON ,  Jae Hun JANG ,  Se Jung KWON ,  Byeongwook KIM ,  Baeseong PARK ,  Dongsoo LEE

IPC: G06F9/50 ,  H03M13/00 ,  H03M13/13

Abstract: Disclosed is an accelerator device which includes an interface circuit that communicates with an external device, a memory that stores first data received through the interface circuit, a polar encoder that performs polar encoding with respect to the first data provided from the memory and to output a result of the polar encoding as second data, and an accelerator core that loads the second data. The first data are compressed weight data, the second data are decompressed weight data, the accelerator core is configured to perform machine learning-based inference based on the second data, and the first data are variable in length.

公开(公告)号：US20250103288A1

公开(公告)日：2025-03-27

申请号：US18818742

申请日：2024-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hun JANG ,  Hong Rak SON ,  Dong-Min SHIN ,  JongYoon YOON ,  Younho JEON ,  Sejung KWON ,  Byeoungwook KIM ,  Baeseong PARK ,  Mankeun SEO ,  Byungmin AHN ,  Dongsoo LEE

IPC: G06F7/485 ,  G06F5/01 ,  G06F7/22

Abstract: Disclosed is an accelerator performing an accumulation operation on a plurality of data, each being a floating point type. A method of operating the accelerator includes loading first data, finding a first exponent, which is a maximum value among exponents of the first data, generating aligned first fractions by performing a bit shift on first fractions of the first data based on the first exponent, and generating a first accumulated value by an accumulation operation on the aligned first fractions, loading second data, finding a second exponent, which is a maximum value among exponents of the second data, and generating a first aligned accumulated value by a bit shift on the first accumulated value, generating aligned second fractions by a bit shift on second fractions of the second data, and generating a second accumulated value by an accumulation operation on the aligned second fractions and the first aligned accumulated value.

公开(公告)号：US20250117440A1

公开(公告)日：2025-04-10

申请号：US18817733

申请日：2024-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hun JANG ,  Hong Rak SON ,  Dong-Min SHIN ,  JongYoon YOON ,  Jihoon LIM ,  Younho JEON ,  Dongsoo LEE ,  Sejung KWON ,  Byeoungwook KIM ,  Baeseong PARK

IPC: G06F17/16 ,  G06F5/01

Abstract: At least one embodiment provides a computing device including: a controller that receives first input data of a first data type and second input data of a second data type different from the first data type, and outputs a first signal representing the first data type, a second signal representing the second data type, and a clock signal based on the number of bits of the first input data and the second input data, and a computing circuit that performs a multiplication computation the first input data and the second input data based on the first signal, the second signal, and the clock signal and generates output data.