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公开(公告)号：US20200159618A1
公开(公告)日：2020-05-21
申请号：US16405427
申请日：2019-05-07
发明人： Eun Chu OH , Young-jin Cho , Young-geun Lee
摘要： A memory controller is provided. The memory controller includes an error correction code (ECC) circuit configured to correct an error of a read codeword provided from a memory device, the ECC circuit including: a codeword combination generator configured to receive a first read codeword including a plurality of first read codeword bit values that are read from a first region of the memory device, generate a change codeword by changing values of one or more of the plurality of first read codeword bit values, and provide a codeword combination including the change codeword; and an ECC decoder including a plurality of ECC engines, wherein the ECC decoder is configured to perform ECC decoding in parallel on a plurality of codewords included in the codeword combination.
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2.发明申请OPERATING METHOD OF NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY SYSTEM 有权非易失性存储器件和非易失性存储器系统的操作方法公开(公告)号：US20150220283A1
公开(公告)日：2015-08-06
申请号：US14616153
申请日：2015-02-06
发明人： Eun Chu OH , JongHa KIM , Junjin KONG , Hong Rak SON
IPC分类号： G06F3/06
CPC分类号： G06F3/0656 , G06F3/061 , G06F3/0679 , G06F12/00 , G06F12/0246
摘要： An operating method of a nonvolatile memory device which includes receiving a plurality of sub-page data and a write command from an external device; performing a pre-main program operation such that at least one of the plurality of sub-page data is stored in the second plurality of memory cells included in the main region; performing a buffered program operation such that other received sub-page data is stored in the first plurality of memory cells included in the buffer region; and performing a re-main program operation such that the received sub-page data subjected to the buffered program operation at the buffer region is stored in the second plurality of memory cells subjected to the pre-main program operation.
摘要翻译： 一种非易失性存储器件的操作方法，包括从外部设备接收多个子页面数据和写入命令; 执行预主程序操作，使得所述多个子页数据中的至少一个存储在所述主区域中包括的所述第二多个存储单元中; 执行缓冲的程序操作，使得其他接收的子页数据存储在包括在缓冲区中的第一多个存储单元中; 以及执行重主程序操作，使得经受缓冲区域缓冲的程序操作的接收到的子页数据被存储在经受主程序编程操作的第二多个存储单元中。
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公开(公告)号：US20230197158A1
公开(公告)日：2023-06-22
申请号：US17810777
申请日：2022-07-05
发明人： Eun Chu OH , Junyeong SEOK , Younggul SONG
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C11/5671 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/0483
摘要： A nonvolatile memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of word-lines, a plurality of memory cells provided in a plurality of channel holes and a word-line cut region extending in a first horizontal direction and dividing the word-lines into a plurality of memory blocks. A plurality of target memory cells coupled to each of the plurality of word-lines are grouped into outer cells and inner cells based on a location index of each of the plurality of memory cells. The control circuit controls a program operation on target memory cells coupled to a target word-line of the plurality of word-lines such that each of the outer cells stores a first number of bits and each of the inner cells stores a second number of bits. The second number is a natural number greater than the first number.
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公开(公告)号：US20220172786A1
公开(公告)日：2022-06-02
申请号：US17675085
申请日：2022-02-18
发明人： Dong Jin SHIN , Ji Su KIM , Dae Seok BYEON , Ji Sang LEE , Jun Jin KONG , Eun Chu OH
摘要： A storage device including, a plurality of non-volatile memories configured to include a memory cell region including at least one first metal pad; and a peripheral circuit region including at least one second metal pad and vertically connected to the memory cell region by the at least one first metal pad and the at least one second metal pad, and a controller connected to the plurality of non-volatile memories through a plurality of channels and configured to control the plurality of non-volatile memories, wherein the controller selects one of a first read operation mode and a second read operation mode and transfers a read command corresponding to the selected read operation mode to the plurality of non-volatile memories, wherein one sensing operation is performed to identify one program state among program sates in the first read operation mode, and wherein at least two sensing operations are performed to identify the one program state among the program states in the second read operation mode.
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公开(公告)号：US20210005271A1
公开(公告)日：2021-01-07
申请号：US17029265
申请日：2020-09-23
发明人： Dong Jin SHIN , Ji Su KIM , Dae Seok BYEON , Ji Sang LEE , Jun Jin KONG , Eun Chu OH
摘要： A storage device including, a plurality of non-volatile memories configured to include a memory cell region including at least one first metal pad; and a peripheral circuit region including at least one second metal pad and vertically connected to the memory cell region by the at least one first metal pad and the at least one second metal pad, and a controller connected to the plurality of non-volatile memories through a plurality of channels and configured to control the plurality of non-volatile memories, wherein the controller selects one of a first read operation mode and a second read operation mode and transfers a read command corresponding to the selected read operation mode to the plurality of non-volatile memories, wherein one sensing operation is performed to identify one program state among program sates in the first read operation mode, and wherein at least two sensing operations are performed to identify the one program state among the program states in the second read operation mode.
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公开(公告)号：US20240069789A1
公开(公告)日：2024-02-29
申请号：US18136041
申请日：2023-04-18
发明人： Eun Chu OH , Beomkyu SHIN
CPC分类号： G06F3/0655 , G06F3/0604 , G06F3/0679 , G06F12/0253
摘要： The present disclosure provides storage devices and methods for operating the same. In some embodiments, a storage device includes a non-volatile memory including a plurality of sub-blocks that are independently erasable, and a processor configured to control a garbage collection operation on the plurality of sub-blocks. The plurality of sub-blocks includes a plurality of first sub-blocks that have a first block size and a plurality of second sub-blocks that have a second block size. The second block size is different from the first block size. The processor is further configured to select a victim sub-block with a lowest ratio of a valid page count to an invalid page count from among the plurality of sub-blocks, and copy a valid page of the victim sub-block to a target sub-block from among the plurality of sub-blocks.
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公开(公告)号：US20230060469A1
公开(公告)日：2023-03-02
申请号：US17854287
申请日：2022-06-30
发明人： Eun Chu OH , Junyeong SEOK , Younggul SONG , Byungchul JANG , Joonsung LIM
IPC分类号： H01L23/00 , H01L25/065 , H01L25/18 , G06F11/10
摘要： A three-dimensional (3D) storage device using wafer-to-wafer bonding is disclosed. In the storage device, a first chip including a peripheral circuit region including a first control logic circuit configured to control operation modes of a nonvolatile memory (NVM) device is wafer-bonded with a second chip including 3D arrays of NVM cells, and a memory controller includes a third chip including a control circuit region. The control circuit region of the third chip includes a second control logic circuit associated with operation conditions of the NVM device, and the second control logic circuit includes a serializer/deserializer (SERDES) interface configured to share random access memory (RAM) in the memory controller and transmit and receive data to and from the NVM device.
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公开(公告)号：US20200152276A1
公开(公告)日：2020-05-14
申请号：US16744763
申请日：2020-01-16
发明人： Dong Jin SHIN , Ji Su KIM , Dae Seok BYEON , Ji Sang LEE , Jun Jin KONG , Eun Chu OH
摘要： A non-volatile memory device including: a page buffer configured to latch a plurality of page data constituting one bit page of a plurality of bit pages, and a control logic configured to compare results of a plurality of read operations performed in response to a high-priority read signal set to select one of a plurality of read signals included in the high-priority read signal set as a high-priority read signal, and determine a low-priority read signal corresponding to the high-priority read signal, wherein the high-priority read signal set is for reading high-priority page data, and the low-priority read signal is for reading low-priority page data.
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公开(公告)号：US20240168669A1
公开(公告)日：2024-05-23
申请号：US18239576
申请日：2023-08-29
发明人： Eun Chu OH , Beomkyu SHIN
IPC分类号： G06F3/06
CPC分类号： G06F3/064 , G06F3/0604 , G06F3/0652 , G06F3/0679
摘要： A non-volatile memory device is provided. The non-volatile memory device includes: sub-blocks provided on a substrate. The sub-blocks include: a first sub-block connected to a first word line group including a first number of word lines; and a second sub-block connected to a second word line group including a second number of word lines. The first sub-block includes: at least one first memory cell storing M-bit data; and second memory cells each storing N-bit data. The second sub-block includes: at least one third memory cell storing K-bit data; and fourth memory cells each storing L-bit data. M, N, K, and L are positive integers, N is greater than M, and L is greater than K. The first number and the second number are different, and the at least one first memory cell and the at least one third memory cell include different numbers of memory cells.
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公开(公告)号：US20230038363A1
公开(公告)日：2023-02-09
申请号：US17848844
申请日：2022-06-24
发明人： Eun Chu OH , Byungchul JANG , Junyeong SEOK , Younggul SONG , Joonsung LIM
IPC分类号： H01L23/00 , H01L25/065 , H01L25/18
摘要： Provided is a three-dimensional storage device using wafer-to-wafer bonding. A storage device includes a first chip including a first substrate and a peripheral circuit region including a first control logic circuit configured to control operation modes of the non-volatile memory device and a second chip including a second substrate and three-dimensional arrays of non-volatile memory cells. The second chip may be vertically stacked on the first chip so that a first surface of the first substrate faces a first surface of the second substrate, and a second control logic circuit is configured to control operation conditions of the non-volatile memory device and is arranged on a second surface of the second substrate, the second surface of the second substrate being opposite to the first surface of the second substrate of the second chip.
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