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公开(公告)号:US20190132008A1
公开(公告)日:2019-05-02
申请号:US15956960
申请日:2018-04-19
发明人: Jae Hun JANG , Dong-Min SHIN , Heon Hwa CHEONG , Jun Jin KONG , Hong Rak SON , Se Jin LIM
摘要: A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an ith operation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the ith operation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.
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公开(公告)号:US20210281280A1
公开(公告)日:2021-09-09
申请号:US17314768
申请日:2021-05-07
发明人: Jae Hun JANG , Dong-Min SHIN , Heon Hwa CHEONG , Jun Jin KONG , Hong Rak SON , Se Jin LIM
摘要: A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an ith operation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the ith operation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.
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