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1.发明申请公开(公告)号：US20190158116A1
公开(公告)日：2019-05-23
申请号：US16024017
申请日：2018-06-29
发明人： Myung-Kyu LEE , Jae-Hong KIM , Ki-Jun LEE , Jun-Jin KONG , Hong-Rak SON , Se-Jin LIM , Young-Jun HWANG
摘要： A method of decoding a low density parity check (LDPC) code, includes dividing a parity check matrix of the LDPC code, into a plurality of sub blocks. The method further includes, for each of a plurality of decoding iterations, performing a node operation of each of target sub blocks among the plurality of sub blocks, the target sub blocks corresponding to a present decoding iteration among the plurality of decoding iterations, in a decoding schedule, estimating a reliability of each of the target sub blocks, based on a result of the node operation of each of the target sub blocks, and adjusting the decoding schedule, based on the reliability of each of the target sub blocks.
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公开(公告)号：US20190340067A1
公开(公告)日：2019-11-07
申请号：US16217249
申请日：2018-12-12
发明人： DAE-HYUN KIM , Yong-Gyu CHU , Jun Jin KONG , Ki-Jun LEE , Myung-Kyu LEE
IPC分类号： G06F11/10 , G11C29/52 , G06F13/16 , H01L25/065 , G11C11/401
摘要： A semiconductor memory device includes: a memory cell array including a plurality of memory cells; an error correction code (ECC) engine configured to detect and/or correct at least one error bit in read data and configured to generate a decoding status flag indicative of whether the at least one error bit is detected and/or corrected, wherein the read data is read from the memory cell array; a channel interface circuit configured to receive the read data and the decoding status flag from the ECC engine and configured to transmit the read data and the decoding status flag to a memory controller, wherein the channel interface circuit is configured to transmit the decoding status flag to the memory controller through a pin; and a control logic circuit configured to control the ECC engine and the channel interface circuit in response to an address and a command from the memory controller.
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3.发明申请公开(公告)号：US20150263767A1
公开(公告)日：2015-09-17
申请号：US14645073
申请日：2015-03-11
发明人： Dong-Min SHIN , Jun-jin KONG , Ki-Jun LEE , Myung-Kyu LEE , Kyeong-Cheol YANG , Seung-Chan LIM
IPC分类号： H03M13/45
CPC分类号： H03M13/13 , H03M13/134
摘要： A list decoding method for a polar code includes generating a tree-type decoding graph for input codeword symbols; the generating a tree-type decoding graph including, generating a decoding path list to which a decoding edge is added based on a reliability of a decoding path, the decoding path list being generated such that, among decoding paths generated based on the decoding edge, decoding paths within a threshold number of critical paths survive within the decoding path list in an order of high likelihood probability, and determining an estimation value, which corresponds to a decoding path having a maximum likelihood probability from among decoding paths of the decoding path list, as an information word.
摘要翻译： 用于极性码的列表解码方法包括：生成用于输入码字符号的树型解码图; 生成树型解码图，包括：基于解码路径的可靠性生成解码边缘被添加到的解码路径列表，生成解码路径列表，使得在基于解码边缘生成的解码路径中， 在所述解码路径列表内以高似然概率的顺序在阈值数量的关键路径内解码路径，并且从所述解码路径列表的解码路径中确定对应于具有最大似然概率的解码路径的估计值， 作为信息词。
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公开(公告)号：US20210303395A1
公开(公告)日：2021-09-30
申请号：US17344180
申请日：2021-06-10
发明人： Dae-Hyun KIM , Yong-Gyu CHU , Jun Jin KONG , Ki-Jun LEE , Myung-Kyu LEE
IPC分类号： G06F11/10 , G11C29/52 , G06F13/16 , G11C11/401 , H01L25/065
摘要： A semiconductor memory device includes: a memory cell array including a plurality of memory cells; an error correction code (ECC) engine configured to detect and/or correct at least one error bit in read data and configured to generate a decoding status flag indicative of whether the at least one error bit is detected and/or corrected, wherein the read data is read from the memory cell array; a channel interface circuit configured to receive the read data and the decoding status flag from the ECC engine and configured to transmit the read data and the decoding status flag to a memory controller, wherein the channel interface circuit is configured to transmit the decoding status flag to the memory controller through a pin; and a control logic circuit configured to control the ECC engine and the channel interface circuit in response to an address and a command from the memory controller.
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