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公开(公告)号：US20220100622A1
公开(公告)日：2022-03-31
申请号：US17245568
申请日：2021-04-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jooyong PARK , Minsu KIM , Daeseok BYEON , Pansuk KWAK
Abstract: A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.
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公开(公告)号：US20210074596A1
公开(公告)日：2021-03-11
申请号：US16846724
申请日：2020-04-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Taehyo KIM , Daeseok BYEON , Chanho KIM
IPC: H01L21/66 , G01N21/95 , H01L23/544
Abstract: A semiconductor device includes a semiconductor die, a semiconductor integrated circuit, an outer crack detection structure, a plurality of inner crack detection structures and a plurality of path selection circuits. The semiconductor die includes a central region and an edge region surrounding the central region. The semiconductor integrated circuit is in a plurality of sub regions of the central region. The outer crack detection structure is in the edge region. The plurality of inner crack detection structures are respectively in the plurality of sub regions, respectively. The path selection circuits are configured to control an electrical connection between the outer crack detection structure and the plurality of inner crack detection structures. A crack in the central region in addition to a crack in the edge region may be detected efficiently through selective electrical connection of the outer crack detection structure and the inner crack detection structures.
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公开(公告)号：US20200211656A1
公开(公告)日：2020-07-02
申请号：US16817043
申请日：2020-03-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Eun Chu OH , Pilsang YOON , Jun Jin KONG , Jisu KIM , Hong Rak SON , Jinbae BANG , Daeseok BYEON , Taehyun SONG , Dongjin SHIN , Dongsup JIN
Abstract: An method of operating a nonvolatile memory device including a plurality of memory cells comprises receiving a read command from an external device, in response to the read command, performing, based on a reference voltage, a first cell counting operation with respect to the plurality of memory cells, adjusting at least one read voltage of first through nth read voltages (where n is a natural number greater than 1) based on a first result of the first cell counting operation, and performing, based on the adjusted at least one read voltage, a read operation corresponding to the read command with respect to the plurality of memory cells.
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公开(公告)号：US20180294036A1
公开(公告)日：2018-10-11
申请号：US16003729
申请日：2018-06-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Eun Chu OH , Pilsang YOON , Jun Jin KONG , Jisu KIM , Hong Rak SON , Jinbae BANG , Daeseok BYEON , Taehyun SONG , Dongjin SHIN , Dongsup JIN
CPC classification number: G11C16/28 , G11C11/5628 , G11C11/5642 , G11C11/5671 , G11C16/04 , G11C16/0466 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3495 , G11C29/021 , G11C29/028 , G11C29/50004 , G11C2029/5004 , G11C2211/563 , G11C2211/5634
Abstract: An method of operating a nonvolatile memory device including a plurality of memory cells comprises receiving a read command from an external device, in response to the read command, performing, based on a reference voltage, a first cell counting operation with respect to the plurality of memory cells, adjusting at least one read voltage of first through nth read voltages (where n is a natural number greater than 1) based on a first result of the first cell counting operation, and performing, based on the adjusted at least one read voltage, a read operation corresponding to the read command with respect to the plurality of memory cells.
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公开(公告)号：US20150270005A1
公开(公告)日：2015-09-24
申请号：US14536843
申请日：2014-11-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yoon-Hee CHOI , Daeseok BYEON , Byunggil JEON
CPC classification number: G11C16/08 , G11C8/08 , G11C8/18 , G11C16/3454 , G11C29/025 , G11C29/50012 , G11C2029/1202
Abstract: An operating method of a memory system which includes a nonvolatile memory device including memory cells connected to a plurality of word lines, the operating method including pre-charging a selected one of the plurality of word lines; detecting a variation in a voltage or a current on the selected word line after the selected word line is floated; generating runtime failure information according to the detected variation; and determining a state of the selected word line or a state of a memory block including the selected word line, based on the runtime failure information.
Abstract translation: 一种存储器系统的操作方法，包括：非易失性存储器件，其包括连接到多个字线的存储器单元，所述操作方法包括对所述多个字线中的所选择的一个字线进行预充电; 在所选择的字线浮动之后检测所选字线上的电压或电流的变化; 根据检测到的变化产生运行时故障信息; 以及基于所述运行时故障信息来确定所选字线的状态或包括所选字线的存储块的状态。
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Patent Agency Ranking
公开(公告)号：US20240306402A1
公开(公告)日：2024-09-12
申请号：US18375173
申请日：2023-09-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Takuya FUTATSUYAMA , Daeseok BYEON
CPC classification number: H10B80/00 , G11C16/0483 , G11C16/16 , G11C16/3445 , H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/08145 , H01L2224/80006 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/14511
Abstract: In some embodiments, a semiconductor memory device includes a peripheral circuit structure, and a first and a second cell array structure. The peripheral circuit structure includes a circuit board, a peripheral circuit on the circuit board, a first insulating layer, and a plurality of first bonding pads on the first insulating layer. The first cell array structure includes a first memory cell array, a first conductive plate structure, a second insulating layer, and pluralities of second and third bonding pads on the second insulating layer. The second cell array structure includes a second memory cell array, a second conductive plate structure, a third insulating layer, and a plurality of fourth bonding pads on the third insulating layer. The first cell array structure and the second cell array structure are sequentially stacked in a vertical direction on the peripheral circuit structure.
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公开(公告)号：US20240194265A1
公开(公告)日：2024-06-13
申请号：US18386472
申请日：2023-11-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Gyosoo CHOO , Daeseok BYEON
IPC: G11C16/08 , G11C5/06 , G11C16/04 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/27 , H10B43/35 , H10B43/40
CPC classification number: G11C16/08 , G11C5/063 , G11C16/0483 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/27 , H10B43/35 , H10B43/40
Abstract: Memory devices having an asymmetric page buffer array architecture are provided. The memory device includes a memory cell array in which each of plural memory planes is included in a cell array structure, and a row decoder array and a page buffer array included in a peripheral circuit structure vertically overlap the cell array structure. The row decoder array is buried in a region vertically overlapping a word line step region of the cell array structure and a partial region of a memory cell array adjacent to the word line step region. In the page buffer array, bit lines of a partial region of the memory cell array in which the row decoder array is buried are connected to a first page buffer array, and bit lines not included in the partial region are connected to a second page buffer array.
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公开(公告)号：US20240153830A1
公开(公告)日：2024-05-09
申请号：US18139707
申请日：2023-04-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Gyosoo CHOO , Daeseok BYEON , Sunghun KIM
CPC classification number: H01L22/34 , G01R31/2607 , H10B80/00
Abstract: A semiconductor device includes a semiconductor die, a detection structure, a path control circuit and a detection circuit. The semiconductor die includes a central region in which a semiconductor integrated circuit is provided and an external region surrounding the central region. The detection structure is provided in the external region. The path control circuit includes a plurality of switches that controls electrical connection of the detection structure. The detection circuit determines whether a defect is present in the semiconductor die and a location of the defect based on a difference signal. The difference signal corresponds to a difference between a forward direction test output signal and a backward direction test output signal obtained by propagating a test input signal through the detection structure in a forward direction and a backward direction, respectively, via the path control circuit.
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19.发明公开公开(公告)号：US20230165008A1
公开(公告)日：2023-05-25
申请号：US18045971
申请日：2022-10-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Changbum KIM , Sunghoon KIM , Daeseok BYEON
IPC: H01L27/11573 , H01L23/535 , H01L27/11556 , H01L27/11529 , H01L27/11582 , G11C16/24 , G11C16/08
CPC classification number: H01L27/11573 , H01L23/535 , H01L27/11556 , H01L27/11529 , H01L27/11582 , G11C16/24 , G11C16/08
Abstract: A memory device includes a first lower semiconductor layer and a second lower semiconductor layer. The first lower semiconductor layer is disposed below a first upper semiconductor layer including a first memory cell array. The first lower semiconductor layer includes a first page buffer electrically connected to the first memory cell array. The second lower semiconductor layer is disposed below a second upper semiconductor layer includes a second memory cell array and disposed adjacent to the first upper semiconductor layer in a first direction. The second lower semiconductor layer includes a first portion of a second page buffer electrically connected to the second memory cell array and being disposed adjacent to the first lower semiconductor layer in the first direction. The first lower semiconductor layer further includes a second portion of the second page buffer different from the first portion.
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公开(公告)号：US20230041064A1
公开(公告)日：2023-02-09
申请号：US17709910
申请日：2022-03-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Changyeon YU , Pansuk KWAK , Daeseok BYEON
Abstract: A semiconductor device includes a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including select transistors and memory cells; pass transistors configured to provide select signals to select lines connected to a selected memory block; and ground transistors configured to supply a first voltage to select lines connected to unselected memory blocks. The ground transistors include at least one common gate structure, at least one common active region, and individual active regions, and each of the common gate structure and the common active region are shared by two or more ground transistors, among the ground transistors. The common gate structure is between the common active region and the individual active regions, and includes a first region extending in a first direction and a second region extending in a second direction, intersecting the first direction.
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