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公开(公告)号：US20230198386A1
公开(公告)日：2023-06-22
申请号：US18168936
申请日：2023-02-14
发明人： Vikas Rana , Marco Pasotti , Fabio De Santis
IPC分类号： H02M3/07
摘要： A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.
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公开(公告)号：US20230110870A1
公开(公告)日：2023-04-13
申请号：US17490976
申请日：2021-09-30
发明人： Laura Capecchi , Marcella Carissimi , Marco Pasotti , Vikas Rana , Vivek Tyagi
摘要： A system and method for operating a memory cell is provided. A non-volatile memory storage device includes an array of memory cells of differential or single-ended type. In an embodiment, a regulator is coupled to a sense amplifier. The regulator is configured to generate a voltage to gate terminals of one or two transistors of the sense amplifier. In the differential type, the voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a maximum current flowing in a memory cell being in a RESET state and a fixed current. In the single-ended type, the regulated voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a fixed current and the reference current generated by the reference current source across temperature.
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公开(公告)号：US20220352817A1
公开(公告)日：2022-11-03
申请号：US17866372
申请日：2022-07-15
发明人： Vikas Rana , Marco Pasotti , Fabio De Santis
IPC分类号： H02M3/07
摘要： A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.
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公开(公告)号：US20210366554A1
公开(公告)日：2021-11-25
申请号：US17306266
申请日：2021-05-03
摘要： An embodiment non-volatile memory device includes an array of memory cells in rows and columns; a plurality of local bitlines, the memory cells of each column being coupled to a corresponding local bitline; a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines; a plurality of program driver circuits, each having a corresponding output node and injecting a programming current in the corresponding output node, each output node coupleable to a corresponding subset of main bitlines. Each program driver circuit further includes a corresponding limiter circuit that is electrically coupled, for each main bitline of the corresponding subset, to a corresponding sense node whose voltage depends, during writing, on the voltage on the corresponding main bitline. Each limiter circuit turns off the corresponding programming current, in case the voltage on any of the corresponding sense nodes overcomes a reference voltage.
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15.发明授权公开(公告)号：US11070128B2
公开(公告)日：2021-07-20
申请号：US16715209
申请日：2019-12-16
发明人： Vikas Rana , Shivam Kalla
摘要： A charge pump circuit generates a charge pump output signal at a first node and is enabled by a charge pump control signal. A diode has first and second terminals coupled to first and second nodes. A comparator has an inverting input coupled to the second node and a non-inverting input coupled to a third node, and causes generation of the charge pump control signal. A first current mirror produces a first current at the second node, and a second current mirror produces a second current (equal in magnitude to the first current) at the third node. The first terminal and second terminals may be a cathode and an anode. The first current mirror may be a current sink sinking a first current from the second node. The second current mirror may be current source sourcing a second current (equal in magnitude to the first current) to the third node.
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公开(公告)号：US10658364B2
公开(公告)日：2020-05-19
申请号：US15908575
申请日：2018-02-28
发明人： Fabio De Santis , Vikas Rana
IPC分类号： H01L27/105 , H01L27/11521 , G11C29/00 , H01L27/112 , H01L27/11519 , H01L27/11558 , G11C16/04 , H01L21/66
摘要： According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (“ROM”) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.
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公开(公告)号：US10284201B1
公开(公告)日：2019-05-07
申请号：US15877970
申请日：2018-01-23
发明人： Vikas Rana
IPC分类号： H03L5/00 , H03K19/00 , H03K19/017 , H03K19/0185
摘要： A voltage level shifter is provided. The voltage level shifter includes an input stage and at least one level shifting stage. The input stage receives an input voltage and a complementary input voltage and receives a first supply voltage and a ground voltage. The input stage outputs one of the first supply voltage and the ground voltage over a first output voltage node and a first complementary output voltage node based on the input voltage and the complementary input voltage. A level shifting stage is coupled to the input stage. The level shifting stage receives the first supply voltage and a second supply voltage and outputs one of the ground voltage, the first supply voltage and the second supply voltage over second and third output voltage nodes and second and third complementary output voltage nodes based on voltages of the first output voltage node and the first complementary output voltage node.
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公开(公告)号：US10211727B1
公开(公告)日：2019-02-19
申请号：US16028814
申请日：2018-07-06
发明人： Vikas Rana
IPC分类号： H02M3/18 , H02M3/07 , H01L27/02 , H01L27/06 , H01L27/092
摘要： A voltage multiplier circuit operates in response to a received clock signal to perform a voltage multiplication operation on an input voltage to generate an output voltage. The voltage multiplier circuit includes a pair of intermediate nodes that are capacitively coupled to receive, respectively, opposite phases of a clock signal. A first CMOS driver circuit is coupled to one of the intermediate nodes and has an output configured to generate one phase of a level shifted output clock signal. A second CMOS driver circuit is coupled to another one of the intermediate nodes and has an output configured to generate another phase of the level shifted output clock signal.
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公开(公告)号：US10127990B1
公开(公告)日：2018-11-13
申请号：US15652564
申请日：2017-07-18
发明人： Vikas Rana
摘要： A memory array includes rows and columns with memory cell portion and a dummy cell portion. Bit lines are connected to the memory cells and to the dummy cell portion. The dummy cell portion includes a first row of dummy cells and a second row of dummy cells. The dummy cells in the first row have a first connection to a corresponding bit line of a first bit line group of the bit lines and a second connection to a first source line. The dummy cells in the second row have a first connection to a corresponding bit line of a second bit line group of the plurality of bit lines and a second connection to a second source line. The dummy cells are selectively actuated to couple voltages at the first and second source lines to the first and second bit line groups, respectively, depending on memory operating mode.
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公开(公告)号：US09755621B1
公开(公告)日：2017-09-05
申请号：US15162827
申请日：2016-05-24
发明人： Rohan Sinha , Vikas Rana
IPC分类号： H03L5/00 , H03K3/356 , H03K19/0185
CPC分类号： H03K3/356113 , H03K19/018521
摘要： A level shifting circuit operates at a high voltage level without stressing the transistors. The circuit has the ability to swing between large supply domains. Multiple output voltage levels are supported for the level shifted signal. Additionally, output nodes are stably driven to supply voltage levels that do not vary with respect to process corner and temperature.
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