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    SINGLE POLY, FLOATING GATE, FEW TIME PROGRAMMABLE NON-VOLATILE MEMORY DEVICE AND BIASING METHOD THEREOF
    3.
    发明申请
    SINGLE POLY, FLOATING GATE, FEW TIME PROGRAMMABLE NON-VOLATILE MEMORY DEVICE AND BIASING METHOD THEREOF 有权

    公开(公告)号：US20220319598A1

    公开(公告)日：2022-10-06

    申请号：US17697846

    申请日：2022-03-17

    申请人： STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

    发明人： Roberto Bregoli ,  Vikas Rana

    IPC分类号： G11C16/04 ,  H01L27/11524 ,  H01L27/1156 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

    摘要： In an embodiment a non-volatile memory cell includes a substrate, a first body in the substrate, a second body in the substrate, a first storage transistor having a first conduction region and a second conduction region in the first body, the first and second conduction regions delimiting a first channel region in the first body, a first control gate region in the second body, an insulating region overlying the substrate, a single floating gate region extending on the substrate and embedded in the insulating region, the single floating gate region having a first portion on the first body and a second portion on the second body, the first portion and second portion being connected and electrically coupled, a first selection via extending through the insulating region and electrically coupling the first conduction region with a first conduction node, a second selection via extending through the insulating region and electrically coupling the second conduction region with a second conduction node and a first control via extending though the insulating region and electrically coupling the first control gate region with a first control node.

    Voltage multiplier circuit with a common bulk and configured for positive and negative voltage generation
    5.
    发明授权
    Voltage multiplier circuit with a common bulk and configured for positive and negative voltage generation 有权

    公开(公告)号：US11183924B2

    公开(公告)日：2021-11-23

    申请号：US17021013

    申请日：2020-09-15

    申请人： STMicroelectronics International N.V.

    发明人： Vikas Rana

    IPC分类号： H02M3/07 ,  H03K19/096 ,  G05F1/10

    摘要： A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.

    Circuit for level shifting a clock signal using a voltage multiplier
    7.
    发明授权
    Circuit for level shifting a clock signal using a voltage multiplier 有权

    公开(公告)号：US10050524B1

    公开(公告)日：2018-08-14

    申请号：US15800896

    申请日：2017-11-01

    申请人： STMicroelectronics International N.V.

    发明人： Vikas Rana

    IPC分类号： H02M3/18 ,  H02M3/07 ,  H01L27/092 ,  H01L27/06 ,  H01L27/02

    摘要： A voltage multiplier circuit operates in response to a received clock signal to perform a voltage multiplication operation on an input voltage to generate an output voltage. The voltage multiplier circuit includes a pair of intermediate nodes that are capacitively coupled to receive, respectively, opposite phases of a clock signal. A first CMOS driver circuit is coupled to one of the intermediate nodes and has an output configured to generate one phase of a level shifted output clock signal. A second CMOS driver circuit is coupled to another one of the intermediate nodes and has an output configured to generate another phase of the level shifted output clock signal.

    Word-line driver for memory
    9.
    发明授权
    Word-line driver for memory 有权
    用于内存的字线驱动程序

    公开(公告)号：US09129685B2

    公开(公告)日：2015-09-08

    申请号：US14266468

    申请日：2014-04-30

    申请人： STMicroelectronics International N.V.

    发明人： Vikas Rana

    IPC分类号： G11C11/4193 ,  G11C11/4195 ,  G11C16/14 ,  G11C8/08 ,  G11C16/06 ,  G11C16/26

    CPC分类号： G11C16/14 ,  G11C8/08 ,  G11C16/06 ,  G11C16/26

    摘要： A word-line driver includes first, second and third transistors. The first transistor includes a gate terminal driven by a first group selection signal, a first conduction terminal driven by a second sub-group selection signal and a second conduction terminal coupled to the word-line. The second transistor includes a gate terminal driven by a second group selection signal, a second conduction terminal driven by the second sub-group selection signal, and a first conduction terminal coupled to the word-line. The third transistor includes a gate terminal driven by a third the group selection signal, a first conduction terminal driven by a first sub-group selection signal, and a second conduction terminal coupled to the word-line.

    摘要翻译： 字线驱动器包括第一，第二和第三晶体管。 第一晶体管包括由第一组选择信号驱动的栅极端子，由第二子组选择信号驱动的第一导通端子和耦合到字线的第二导通端子。 第二晶体管包括由第二组选择信号驱动的栅极端子，由第二子组选择信号驱动的第二导通端子和耦合到字线的第一导电端子。 第三晶体管包括由组选择信号的第三组驱动的栅极端子，由第一子组选择信号驱动的第一导通端子和耦合到字线的第二导通端子。