公开(公告)号：US09941369B2

公开(公告)日：2018-04-10

申请号：US15195784

申请日：2016-06-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Julien Delalleau ,  Arnaud Regnier

IPC: H01L29/788 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11521 ,  G11C16/14 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/11524 ,  H01L29/78 ,  G11C16/04 ,  H01L21/306

CPC classification number: H01L29/42328 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/32051 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.

公开(公告)号：US20170179247A1

公开(公告)日：2017-06-22

申请号：US15454184

申请日：2017-03-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau ,  Christian Rivero

IPC: H01L29/423 ,  H01L21/311 ,  H01L29/78 ,  H01L29/08 ,  H01L21/02 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/4236 ,  H01L21/02236 ,  H01L21/28167 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78

Abstract: An integrated MOS transistor is formed in a substrate. The transistor includes a gate region buried in a trench of the substrate. The gate region is surrounded by a dielectric region covering internal walls of the trench. A source region and drain region are situated in the substrate on opposite sides of the trench. The dielectric region includes an upper dielectric zone situated at least partially between an upper part of the gate region and the source and drain regions. The dielectric region further includes a lower dielectric zone that is less thick than the upper dielectric zone and is situated between a lower part of the gate region and the substrate.

公开(公告)号：US09559297B2

公开(公告)日：2017-01-31

申请号：US15214054

申请日：2016-07-19

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe Boivin ,  Julien Delalleau

IPC: H01L43/12 ,  H01L27/24 ,  H01L27/115 ,  H01L27/22 ,  H01L29/423 ,  H01L29/78 ,  H01L45/00 ,  H01L43/02 ,  H01L43/08 ,  H01L21/265 ,  H01L21/762

CPC classification number: H01L43/12 ,  H01L21/26513 ,  H01L21/76224 ,  H01L23/528 ,  H01L27/11507 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463 ,  H01L29/42356 ,  H01L29/7827 ,  H01L43/02 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a method of making a memory on semiconductor substrate, comprising: at least one data line, at least one selection line, at least one reference line, at least one memory cell comprising a select transistor having a control gate connected to the selection line, a first conduction terminal connected to a variable impedance element, the select transistor and the variable impedance element coupling the reference line to the data line, the select transistor comprising an embedded vertical gate produced in a trench formed in the substrate, and a channel region opposite a first face of the trench, between a first deep doped region and a second doped region on the surface of the substrate coupled to the variable impedance element.

Abstract translation: 本公开涉及一种在半导体衬底上制造存储器的方法，包括：至少一条数据线，至少一条选择线，至少一条参考线，至少一个存储单元，包括选择晶体管，其具有连接到 所述选择线，连接到可变阻抗元件的第一导电端子，所述选择晶体管和所述参考线耦合到所述数据线的所述可变阻抗元件，所述选择晶体管包括在形成在所述衬底中的沟槽中产生的嵌入垂直栅极，以及 与沟槽的第一面相对的沟道区，位于耦合到可变阻抗元件的衬底表面上的第一深掺杂区和第二掺杂区之间。

公开(公告)号：US20170012104A1

公开(公告)日：2017-01-12

申请号：US15068732

申请日：2016-03-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau ,  Christian Rivero

IPC: H01L29/423 ,  H01L21/306 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/4236 ,  H01L21/02236 ,  H01L21/28167 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78

Abstract: An integrated MOS transistor is formed in a substrate. The transistor includes a gate region buried in a trench of the substrate. The gate region is surrounded by a dielectric region covering internal walls of the trench. A source region and drain region are situated in the substrate on opposite sides of the trench. The dielectric region includes an upper dielectric zone situated at least partially between an upper part of the gate region and the source and drain regions. The dielectric region further includes a lower dielectric zone that is less thick than the upper dielectric zone and is situated between a lower part of the gate region and the substrate.

Abstract translation: 在基板中形成集成的MOS晶体管。 晶体管包括掩埋在衬底的沟槽中的栅极区域。 栅极区域被覆盖沟槽内壁的电介质区域围绕。 源极区域和漏极区域位于沟槽的相对侧上的衬底中。 电介质区域包括至少部分地位于栅极区域的上部与源极和漏极区域之间的上部电介质区域。 所述电介质区域还包括下部电介质区域，所述下部电介质区域比所述上部电介质区域厚，并且位于所述栅极区域的下部和所述衬底之间。

公开(公告)号：US11581270B2

公开(公告)日：2023-02-14

申请号：US17014058

申请日：2020-09-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau ,  Christian Rivero

IPC: H01L23/52 ,  H01L23/00 ,  H01L23/528 ,  H01L29/06 ,  H01L27/088 ,  H01L29/10 ,  H01L27/02 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/45

Abstract: An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.

公开(公告)号：US10804222B2

公开(公告)日：2020-10-13

申请号：US16036639

申请日：2018-07-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau ,  Christian Rivero

IPC: H01L29/08 ,  H01L23/00 ,  H01L23/528 ,  H01L29/06 ,  H01L27/088 ,  H01L29/10 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/45

Abstract: An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.

公开(公告)号：US10714583B2

公开(公告)日：2020-07-14

申请号：US16037095

申请日：2018-07-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Guilhem Bouton ,  Pascal Fornara ,  Julien Delalleau

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/28 ,  H01L21/8234

Abstract: A MOS transistor is produced on and in an active zone which includes a source region and a drain region. The active zone is surrounded by an insulating region. A conductive gate region of the transistor has two flanks which extend transversely to a source-drain direction, and the conductive gate region overlaps two opposite edges of the active zone act overlap zones. The conductive gate region includes, at a location of at least one overlap zone, at least one conductive tag which projects from at least one flank at a foot of the conductive gate region. The conductive tag covers a part of the active zone and a part of the insulating region.

公开(公告)号：US10593772B2

公开(公告)日：2020-03-17

申请号：US16036240

申请日：2018-07-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Julien Delalleau

IPC: H01L29/423 ,  H01L27/11521 ,  H01L29/788 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11524

Abstract: A MOS transistor located in and on a semiconductor substrate has a drain region, a source region and a conductive gate region. The conductive gate region includes a first conductive gate region that is insulated from the semiconductor substrate and a second conductive gate region that is insulated from and located above the first conductive gate region. A length of the first conductive gate region, measured in the drain-source direction, is greater than a length of the second conductive gate region, also measured in the drain-source direction. The first conductive gate region protrudes longitudinally in the drain-source direction beyond the second conductive gate region at least on one side of the second conductive gate region so as to extend over at least one of the source and drain regions.

公开(公告)号：US10074429B2

公开(公告)日：2018-09-11

申请号：US15895732

申请日：2018-02-13

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/26 ,  G11C16/12 ,  G11C16/14 ,  H01L27/11556 ,  H01L27/11521

Abstract: A non-volatile memory cell includes a selection transistor having an insulated selection gate embedded in a semiconducting substrate region. A semiconducting source region contacts a lower part of the insulated selection gate. A state transistor includes a floating gate having an insulated part embedded in the substrate region above an upper part of the insulated selection gate, a semiconducting drain region, and a control gate insulated from the floating gate and located partially above the floating gate. The source region, the drain region, the substrate region, and the control gate are individually polarizable.

公开(公告)号：US20180174655A1

公开(公告)日：2018-06-21

申请号：US15895732

申请日：2018-02-13

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/12 ,  H01L27/11556 ,  H01L27/11521 ,  G11C16/14

CPC classification number: G11C16/0433 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/42336

Abstract: A non-volatile memory cell includes a selection transistor having an insulated selection gate embedded in a semiconducting substrate region. A semiconducting source region contacts a lower part of the insulated selection gate. A state transistor includes a floating gate having an insulated part embedded in the substrate region above an upper part of the insulated selection gate, a semiconducting drain region, and a control gate insulated from the floating gate and located partially above the floating gate. The source region, the drain region, the substrate region, and the control gate are individually polarizable.