公开(公告)号：US11948882B2

公开(公告)日：2024-04-02

申请号：US17964244

申请日：2022-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon Chang ,  Jimin Choi ,  Yeonjin Lee ,  Hyeon-Woo Jang ,  Jung-Hoon Han

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53266

Abstract: The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

公开(公告)号：US11495533B2

公开(公告)日：2022-11-08

申请号：US17153963

申请日：2021-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon Chang ,  Jimin Choi ,  Yeonjin Lee ,  Hyeon-Woo Jang ,  Jung-Hoon Han

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

公开(公告)号：US20240194624A1

公开(公告)日：2024-06-13

申请号：US18512375

申请日：2023-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong Kim ,  Jongmin Lee ,  Jimin Choi

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L24/06 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204

Abstract: A semiconductor chip includes a semiconductor substrate including an active surface and an inactive surface facing the active surface, a multi wiring layer arranged on the active surface of the semiconductor substrate, and including a wiring structure having at least two layers and including a conductive wiring and a dummy wiring, a lower protection layer arranged on a front surface of the multi wiring layer, and including a conductive medium pad connected to the conductive wiring, a plurality of through vias configured to penetrate the semiconductor substrate, and including a plurality of power through vias, a plurality of signal through vias, and a plurality of dummy through vias; and a plurality of back side pads arranged on the inactive surface of the semiconductor substrate, and connected to the plurality of through vias, wherein the plurality of dummy through vias are connected to the wiring structure.

公开(公告)号：US12006144B2

公开(公告)日：2024-06-11

申请号：US17517963

申请日：2021-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeongdam Baek ,  Minsoo Park ,  Seungjun Lee ,  Mingu Chang ,  Byungkook Yoo ,  Hujong Lee ,  Jimin Choi

IPC: B65G1/04 ,  B65G23/22 ,  B65G23/24

CPC classification number: B65G1/0457 ,  B65G23/22 ,  B65G23/24 ,  B65G2201/0297 ,  B65G2812/02148

Abstract: An apparatus for storage of a carrying material, includes: a body frame; a plurality of loading members installed on the body frame and disposed such that a carrying material forms a plurality of layers in upper and lower directions; a driving unit connected to at least one of the plurality of loading members; and an auxiliary coupling unit provided in a portion of the plurality of loading members for attachment and detachment to and from a neighboring loading member, wherein the plurality of loading members are provided with a plurality of first loading members fixedly installed at a lower end portion of the body frame, and a plurality of second loading members disposed above the first loading member and movably installed on the body frame, wherein the driving unit is connected to at least one of the plurality of second loading members, wherein the auxiliary coupling unit includes an electromagnet installed at one end of the second loading members, and a magnetic body installed at the other end of the second loading members and the body frame to correspond to the electromagnet.

公开(公告)号：US11587897B2

公开(公告)日：2023-02-21

申请号：US17143224

申请日：2021-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joongwon Shin ,  Yeonjin Lee ,  Inyoung Lee ,  Jimin Choi ,  Jung-Hoon Han

IPC: H01L23/29 ,  H01L23/31 ,  H01L23/00

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a conductive pad on a first surface of the semiconductor substrate, a passivation layer on the first surface of the semiconductor substrate, the passivation layer having a first opening that exposes the conductive pad, an organic dielectric layer on the passivation layer, the organic dielectric layer having a second opening, and a bump structure on the conductive pad and in the first and second openings. The organic dielectric layer includes a material different from a material of the passivation layer. The second opening is spatially connected to the first opening and exposes a portion of the passivation layer. The bump structure includes a pillar pattern in contact with the passivation layer and the organic dielectric layer.

公开(公告)号：US11476220B2

公开(公告)日：2022-10-18

申请号：US17146550

申请日：2021-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jimin Choi ,  Jung-Hoon Han ,  Yeonjin Lee ,  Jong-Min Lee ,  Jihoon Chang

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L21/66

Abstract: Semiconductor packages may include a semiconductor chip on a substrate and an under-fill layer between the semiconductor chip and the substrate. The semiconductor chip may include a semiconductor substrate including first and second regions, and an interlayer dielectric layer that may cover the semiconductor substrate and may include connection lines. First conductive pads may be on the first region and may be electrically connected to some of the connection lines. Second conductive pads may be on the second region and may be electrically isolated from all of the connection lines. The semiconductor chip may also include a passivation layer that may cover the interlayer dielectric layer and may include holes that may expose the first and second conductive pads, respectively. On the second region, the under-fill layer may include a portion that may be in one of the first holes and contact one of the second conductive pads.

公开(公告)号：US20210366102A1

公开(公告)日：2021-11-25

申请号：US17102700

申请日：2020-11-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suhwan PARK ,  Namil Koo ,  Taeheung Ahn ,  Kwangjun Yoon ,  Jongmin Yoon ,  Ikseon Jeon ,  Jimin Choi

IPC: G06T7/00 ,  G01N21/95 ,  G01N21/956 ,  G06K9/46 ,  G06T7/13 ,  G06T7/70 ,  H01L21/67

Abstract: An inspection apparatus includes a measurement device disposed to be spaced apart from an upper surface of a wafer, an image capturing device configured to capture an image of at least a portion of the measurement device and at least a portion of the upper surface of the wafer, a memory storing an algorithm to measure a distance between the measurement device and the upper surface of the wafer based on the image, and a controller configured to measure the distance between the measurement device and the upper surface of the wafer based on the algorithm, wherein the image includes a measurement region in which the measurement device is displayed, a wafer region in which the wafer is displayed, and a reflective region in which the measurement device being reflected on the upper surface of the wafer is displayed, and wherein the wafer region and the reflective region overlap with each other.

公开(公告)号：US20240189991A1

公开(公告)日：2024-06-13

申请号：US18528515

申请日：2023-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeongdam Baek ,  Hyeonuk Kim ,  Byungkook Yoo ,  Seungjun Lee ,  Mingu Chang ,  Younboo Jung ,  Jaehyuk Cha ,  Jimin Choi ,  Sunoh Kim ,  Kyeongjun Min ,  Donghoon Yang ,  Jiwon Yoon ,  Seungjun Lee ,  Insung Choi

IPC: B25J9/16 ,  B25J9/00

CPC classification number: B25J9/162 ,  B25J9/0009 ,  B25J9/1682

Abstract: An autonomous driving robot includes a storage unit including a housing, which provides a space for storing an article, and a shelf which is provided inside the housing and on which the article is loaded, a manipulator including a linear actuator, and a selective compliance articulated robot arm, which is coupled to the linear actuator, and a transport unit coupled to the storage unit, wherein a plurality of shelves are provided, some of the shelves are provided adjacent to one inner wall of the housing and spaced apart from each other in the vertical direction, and the other shelves are provided adjacent to another inner wall which faces the one inner wall and spaced apart from each other in the vertical direction, and the plurality of shelves extend toward a central portion of the housing, but extend to a point before reaching the central portion of the housing.

公开(公告)号：US20240145317A1

公开(公告)日：2024-05-02

申请号：US18210114

申请日：2023-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joongwon Shin ,  Jongmin Lee ,  Sungyun Woo ,  Nara Lee ,  Yeonjin Lee ,  Jimin Choi

IPC: H01L21/66 ,  G01R31/28 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L22/32 ,  G01R31/2896 ,  H01L23/481 ,  H01L24/05 ,  H01L25/18 ,  H01L25/50 ,  H10B80/00 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/06136 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/014

Abstract: A semiconductor package, includes: a base chip having a front surface and a back surface opposite to the front surface, the base chip including bump pads, wafer test pads, and package test pads, disposed on the front surface; connection structures disposed on the front surface of the base chip and connected to the bump pads; and semiconductor chips stacked on the back surface of the base chip, wherein each of the wafer test pads is smaller than the package test pads.

公开(公告)号：US20240069093A1

公开(公告)日：2024-02-29

申请号：US18174865

申请日：2023-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sehyun Hwang ,  Jongmin Lee ,  Joongwon Shin ,  Jimin Choi

IPC: G01R31/28 ,  H01L23/00 ,  H01L23/50 ,  H01L23/528 ,  H10B80/00

CPC classification number: G01R31/2884 ,  H01L23/50 ,  H01L23/528 ,  H01L24/05 ,  H10B80/00 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/0557 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/14361

Abstract: Provided are a semiconductor chip with a reduced thickness and improved reliability, and a semiconductor package including the semiconductor chip. The semiconductor chip includes a semiconductor substrate, an integrated device layer on the semiconductor substrate, a multi-wiring layer on the integrated device layer, and a pad metal layer of a plurality of pad metal layers on the multi-wiring layer, and having test pads defined therein. The pad metal layers extend in a first direction parallel to a top surface of the semiconductor substrate or in a second direction perpendicular to the first direction. A test pad is a central portion of the pad metal layer and, and an outer portion of the pad metal layer excluding the test pad overlaps the wires in a third direction perpendicular to the top surface of the semiconductor substrate.