公开(公告)号：US20240145317A1

公开(公告)日：2024-05-02

申请号：US18210114

申请日：2023-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joongwon Shin ,  Jongmin Lee ,  Sungyun Woo ,  Nara Lee ,  Yeonjin Lee ,  Jimin Choi

IPC: H01L21/66 ,  G01R31/28 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L22/32 ,  G01R31/2896 ,  H01L23/481 ,  H01L24/05 ,  H01L25/18 ,  H01L25/50 ,  H10B80/00 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/06136 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/014

Abstract: A semiconductor package, includes: a base chip having a front surface and a back surface opposite to the front surface, the base chip including bump pads, wafer test pads, and package test pads, disposed on the front surface; connection structures disposed on the front surface of the base chip and connected to the bump pads; and semiconductor chips stacked on the back surface of the base chip, wherein each of the wafer test pads is smaller than the package test pads.