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    Semiconductor device and method of fabricating the same
    11.
    发明授权
    Semiconductor device and method of fabricating the same 有权

    公开(公告)号：US12302556B2

    公开(公告)日：2025-05-13

    申请号：US17747423

    申请日：2022-05-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dong-Wan Kim ,  Keonhee Park ,  Dong-Sik Park ,  Joonsuk Park ,  Jihoon Chang ,  Hyeon-Woo Jang

    IPC: H01L27/108 ,  H01L21/3213 ,  H10B12/00

    Abstract: Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a substrate including a peripheral block and cell blocks each including a cell center region, a cell edge region, and a cell middle region, and bit lines extending on each cell block in a first direction. The bit lines include center bit lines, middle bit lines, and edge bit lines. The bit line has first and second lateral surfaces opposite to each other in a second direction. The first lateral surface straightly extends along the first direction on the cell center region, the cell middle region, and the cell edge region. The second lateral surface straightly extends along the first direction on the cell center region and the cell edge region, and the second lateral surface extends along a third direction, that intersects the first direction and the second direction, on the cell middle region.

    Semiconductor memory devices having protruding contact portions
    12.
    发明授权
    Semiconductor memory devices having protruding contact portions 有权

    公开(公告)号：US11723191B2

    公开(公告)日：2023-08-08

    申请号：US17192084

    申请日：2021-03-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minsu Choi ,  Myeong-Dong Lee ,  Hyeon-Woo Jang ,  Keunnam Kim ,  Sooho Shin ,  Yoosang Hwang

    IPC: H10B12/00

    CPC classification number: H10B12/34 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/315

    Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device includes a substrate including an active pattern with doped regions, a gate electrode crossing the active pattern between the doped regions, a bit line crossing the active pattern and being electrically connected to one of the doped regions, a spacer on a side surface of the bit line, a first contact coupled to another of the doped regions and spaced apart from the bit line with the spacer interposed therebetween, a landing pad on the first contact, and a data storing element on the landing pad. The another of the doped regions has a top surface, an upper side surface, and a curved top surface that extends from the top surface to the upper side surface. The first contact is in contact with the curved top surface and the upper side surface.

    SEMICONDUCTOR DEVICE
    13.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230045674A1

    公开(公告)日：2023-02-09

    申请号：US17662306

    申请日：2022-05-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyeon-Woo Jang ,  Dong-Wan Kim ,  Keonhee Park ,  Dong-Sik Park ,  Joonsuk Park ,  Jihoon Chang

    IPC: H01L27/108

    Abstract: A semiconductor device may include a substrate including a cell region and a peripheral region, a gate stack on the peripheral region, an interlayer insulating layer on the gate stack, peripheral circuit interconnection lines on the interlayer insulating layer, and an interconnection insulating pattern between the peripheral circuit interconnection lines. The interconnection insulating pattern may include a pair of vertical portions spaced apart from each other in a first direction parallel to a top surface of the substrate and a connecting portion connecting the vertical portions to each other. Each of the vertical portions of the interconnection insulating pattern may have a first thickness at a same level as top surfaces of the peripheral circuit interconnection lines and a second thickness at a same level as bottom surfaces of the peripheral circuit interconnection lines. The first thickness may be substantially equal to the second thickness.

    Semiconductor devices with peripheral gate structures
    14.
    发明授权
    Semiconductor devices with peripheral gate structures 有权

    公开(公告)号：US11502082B2

    公开(公告)日：2022-11-15

    申请号：US16902338

    申请日：2020-06-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ho-In Ryu ,  Taiheui Cho ,  Keunnam Kim ,  Kyehee Yeom ,  Junghwan Park ,  Hyeon-Woo Jang

    IPC: H01L27/105 ,  H01L27/108 ,  H01L29/423 ,  H01L21/768

    Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

    Semiconductor devices with peripheral gate structures
    15.
    发明授权
    Semiconductor devices with peripheral gate structures 有权

    公开(公告)号：US10714478B2

    公开(公告)日：2020-07-14

    申请号：US16532857

    申请日：2019-08-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ho-In Ryu ,  Taiheui Cho ,  Keunnam Kim ,  Kyehee Yeom ,  Junghwan Park ,  Hyeon-Woo Jang

    IPC: H01L27/105 ,  H01L27/108 ,  H01L29/423 ,  H01L21/768

    Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

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