SEMICONDUCTOR DEVICE
    11.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号:US20150060948A1

    公开(公告)日:2015-03-05

    申请号:US14472665

    申请日:2014-08-29

    Abstract: A field plate causes excessive gate capacitance that interferes with high-speed transistor switching. To suppress the excessive gate capacitance, an aperture includes a first side wall positioned on the side of a drain electrode, and a second side wall positioned on the side of a source electrode. A gate electrode at the same time includes a first side surface facing opposite the drain electrode as seen from a plan view. The first side surface of the gate electrode is positioned on the inner side of the first side wall and the second side wall as seen from a flat view. Moreover, a portion of a first field plate is embedded between the first side surface and the first side wall. The gate electrode and the first field plate are electrically insulated by a first insulation member.

    Abstract translation: 场板引起过大的栅极电容干扰高速晶体管切换。 为了抑制过剩的栅极电容,孔包括位于漏极侧的第一侧壁和位于源极侧的第二侧壁。 栅电极同时包括从俯视图看的与漏电极相对的第一侧表面。 从平面看,栅电极的第一侧表面位于第一侧壁和第二侧壁的内侧。 此外,第一场板的一部分嵌入在第一侧面和第一侧壁之间。 栅电极和第一场板由第一绝缘构件电绝缘。

    SEMICONDUCTOR DEVICE
    12.
    发明申请

    公开(公告)号:US20250054884A1

    公开(公告)日:2025-02-13

    申请号:US18932997

    申请日:2024-10-31

    Abstract: A semiconductor device has a semiconductor substrate, a first insulating layer, a first inductor, a second insulating layer, a second inductor, a pad and an annular wiring. The first insulating layer is formed on the semiconductor substrate. The first inductor is directly formed on the first insulating layer. The second insulating layer is formed on the first insulating layer such that the second insulating layer covers the first inductor. The second inductor is directly formed on the second insulating layer such that the second inductor faces the first inductor. The pad is directly formed on the second insulating layer. The pad is electrically connected with the second inductor. The annular wiring is electrically connected with the pad. The annular wiring is spaced apart from the second inductor. The annular wiring surrounds the second inductor without forming a vertex in plan view.

    SEMICONDUCTOR DEVICE
    13.
    发明公开

    公开(公告)号:US20240304524A1

    公开(公告)日:2024-09-12

    申请号:US18664117

    申请日:2024-05-14

    CPC classification number: H01L23/485 H01L29/872

    Abstract: A semiconductor device includes a semiconductor substrate, a buried insulating film, a first conductive film, an insulating layer, a first contact and a second contact. The semiconductor substrate includes a first semiconductor region having a first conductive type and a second semiconductor region having a second conductive type. The buried insulating film surrounds the second semiconductor region in plan view. The first conductive film directly contacts with the first and second semiconductor regions. The first and second contacts overlap with the second semiconductor region in plan view and reach the first conductive film. The first contact is adjacent to the second contact along a first side of the second semiconductor region in plan view. In a direction along the first side, a first distance between the second semiconductor region and the buried insulating film is greater than a second distance between the first contact and the second contact.

    SEMICONDUCTOR DEVICE
    15.
    发明申请

    公开(公告)号:US20230016552A1

    公开(公告)日:2023-01-19

    申请号:US17946368

    申请日:2022-09-16

    Abstract: A semiconductor device includes a semiconductor substrate, a buried insulating film, a first conductive film, an insulating layer, a first contact and a second contact. The semiconductor substrate includes a first semiconductor region having a first conductive type and a second semiconductor region having a second conductive type. The buried insulating film surrounds the second semiconductor region in plan view. The first conductive film directly contacts with the first and second semiconductor regions. The first and second contacts overlap with the second semiconductor region in plan view and reach the first conductive film. The first contact is adjacent to the second contact along a first side of the second semiconductor region in plan view. In a direction along the first side, a first distance between the second semiconductor region and the buried insulating film is greater than a second distance between the first contact and the second contact.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20250118685A1

    公开(公告)日:2025-04-10

    申请号:US18904186

    申请日:2024-10-02

    Abstract: A semiconductor device includes a semiconductor substrate, a multilayer wiring structure formed on the semiconductor substrate, a guard ring formed so as to surround a circuit formation region and penetrate the multilayer wiring structure, and a pad formed on the multilayer wiring structure. A protective film is formed so as to cover the multilayer wiring structure, the guard ring, and the pad. A trench is formed so as to penetrate the protective film and reach an inside of the multilayer wiring structure. The trench is formed so as to surround the guard ring. The guard ring includes a wiring formed on the multilayer wiring structure. The trench is spaced apart from and adjacent to the wiring. A bottom surface of the trench is inclined so as to be continuously deepened in a direction from the circuit formation region toward a peripheral region surrounding the circuit formation region.

    SEMICONDUCTOR DEVICE
    20.
    发明公开

    公开(公告)号:US20230299197A1

    公开(公告)日:2023-09-21

    申请号:US17697393

    申请日:2022-03-17

    CPC classification number: H01L29/78391 H01L29/516

    Abstract: A semiconductor device is provided with an SOI substrate which includes a semiconductor substrate, a ferroelectric layer and a semiconductor layer, and has a first region in which a first MISFET is formed. The first MISFET includes: the semiconductor substrate in the first region; the ferroelectric layer in the first region; the semiconductor layer in the first region; a first gate insulating film formed on the semiconductor layer in the first region; a first gate electrode formed on the first gate insulating film; a first source region located on one side of the first gate electrode and formed in the semiconductor layer in the first region; and a first drain region located on the other side of the first gate electrode and formed in the semiconductor layer in the first region.

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