公开(公告)号：US20170323980A1

公开(公告)日：2017-11-09

申请号：US15658259

申请日：2017-07-24

Applicant: Renesas Electronics Corporation

Inventor： Atsushi AMO

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L27/1157 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/66484 ,  H01L29/66833 ,  H01L29/7831

Abstract: An object is to provide a reliability-improved semiconductor device having a MONOS memory that rewrites data by injecting carriers into a charge storage portion. When a memory gate electrode having a small gate length is formed in order to overlap a carrier injection position in write operation with that in erase operation, each into an ONO film including a charge storage portion, the ONO film is formed in a recess of a main surface of a semiconductor substrate for securing a large channel length. In a step of manufacturing this structure, control gate electrodes are formed by stepwise processing of a polysilicon film by first and second etching and then, the recess is formed in the main surface of the semiconductor substrate on one side of the control gate electrode by second etching.

公开(公告)号：US20190280096A1

公开(公告)日：2019-09-12

申请号：US16282864

申请日：2019-02-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi AMO

IPC: H01L29/423 ,  H01L21/28 ,  H01L27/11568 ,  H01L27/11573

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate having a first surface; a first conductive film that is located over the first surface and is formed to circle in plan view; a second conductive film that is located over the first surface and surrounds the outer periphery of the first conductive film in plan view; a first insulating spacer located between the first conductive film and the second conductive film; a first gate insulating film that is located between the first surface and the first conductive film and the accumulated amount of charges of which changes due to a change in the voltage between the first conductive film and the semiconductor substrate; and a second gate insulating film located between the first surface and the second conductive film.

公开(公告)号：US20180198001A1

公开(公告)日：2018-07-12

申请号：US15914196

申请日：2018-03-07

Applicant: Renesas Electronics Corporation

Inventor： Atsushi AMO

IPC: H01L29/94 ,  H01L27/06 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11573 ,  G11C16/04 ,  H01L29/423

CPC classification number: H01L29/945 ,  G11C16/0466 ,  H01L27/0629 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66181 ,  H01L29/66833 ,  H01L29/792

Abstract: In a semiconductor device including a split gate type MONOS memory, and a trench capacitor element having an upper electrode partially embedded in trenches formed in the main surface of a semiconductor substrate, merged therein, the flatness of the top surface of the upper electrode embedded in the trench is improved. The polysilicon film formed over the semiconductor substrate to form a control gate electrode forming a memory cell of the MONOS memory is embedded in the trenches formed in the main surface of the semiconductor substrate in a capacitor element formation region, thereby to form the upper electrode including the polysilicon film in the trenches.

公开(公告)号：US20160293776A1

公开(公告)日：2016-10-06

申请号：US15043569

申请日：2016-02-14

Applicant: Renesas Electronics Corporation

Inventor： Atsushi AMO

IPC: H01L29/792 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/66484 ,  H01L29/66833 ,  H01L29/7831

Abstract: An object is to provide a reliability-improved semiconductor device having a MONOS memory that rewrites data by injecting carriers into a charge storage portion. When a memory gate electrode having a small gate length is formed in order to overlap a carrier injection position in write operation with that in erase operation, each into an ONO film including a charge storage portion, the ONO film is formed in a recess of a main surface of a semiconductor substrate for securing a large channel length. In a step of manufacturing this structure, control gate electrodes are formed by stepwise processing of a polysilicon film by first and second etching and then, the recess is formed in the main surface of the semiconductor substrate on one side of the control gate electrode by second etching.

Abstract translation: 目的是提供一种可靠性改进的半导体器件，其具有通过将载流子注入电荷存储部分来重写数据的MONOS存储器。 当形成具有较小栅极长度的存储栅极电极，以便在写入操作中的载流子注入位置与擦除操作中的载流子注入位置重叠，每个形成包括电荷存储部分的ONO膜，ONO膜形成在 用于确保大的通道长度的半导体衬底的主表面。 在制造该结构的步骤中，通过第一和第二蚀刻对多晶硅膜进行逐步处理，形成控制栅电极，然后在控制栅电极一侧的半导体衬底的主表面中形成第二凹槽 蚀刻。

公开(公告)号：US20230299197A1

公开(公告)日：2023-09-21

申请号：US17697393

申请日：2022-03-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Eiji TSUKUDA ,  Tohru KAWAI ,  Atsushi AMO

IPC: H01L29/78 ,  H01L29/51

CPC classification number: H01L29/78391 ,  H01L29/516

Abstract: A semiconductor device is provided with an SOI substrate which includes a semiconductor substrate, a ferroelectric layer and a semiconductor layer, and has a first region in which a first MISFET is formed. The first MISFET includes: the semiconductor substrate in the first region; the ferroelectric layer in the first region; the semiconductor layer in the first region; a first gate insulating film formed on the semiconductor layer in the first region; a first gate electrode formed on the first gate insulating film; a first source region located on one side of the first gate electrode and formed in the semiconductor layer in the first region; and a first drain region located on the other side of the first gate electrode and formed in the semiconductor layer in the first region.

公开(公告)号：US20230093724A1

公开(公告)日：2023-03-23

申请号：US17876067

申请日：2022-07-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi AMO ,  Hiraku CHAKIHARA ,  Hiroshi YANAGITA ,  Akio ONO

IPC: H01L21/66 ,  H01L27/11 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51

Abstract: A method of manufacturing a semiconductor device capable of detecting occurrence of a Hi-K disappearance is provided. The method of manufacturing a semiconductor device includes a step of manufacturing a test pattern including a reference resistance, a gate leakage resistance through which a gate leakage current flows and connected in series with the reference resistance, and a step of measuring a change in voltage at a connection node between the reference resistance and the gate leakage resistance caused by the flow of the gate leakage current.

公开(公告)号：US20170323983A1

公开(公告)日：2017-11-09

申请号：US15661649

申请日：2017-07-27

Applicant: Renesas Electronics Corporation

Inventor： Atsushi AMO

IPC: H01L29/94 ,  H01L29/66 ,  H01L29/423 ,  G11C16/04 ,  H01L27/11573 ,  H01L27/06 ,  H01L29/792

CPC classification number: H01L29/945 ,  G11C16/0466 ,  H01L27/0629 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66181 ,  H01L29/66833 ,  H01L29/792

Abstract: In a semiconductor device including a split gate type MONOS memory, and a trench capacitor element having an upper electrode partially embedded in trenches formed in the main surface of a semiconductor substrate, merged therein, the flatness of the top surface of the upper electrode embedded in the trench is improved. The polysilicon film formed over the semiconductor substrate to form a control gate electrode forming a memory cell of the MONOS memory is embedded in the trenches formed in the main surface of the semiconductor substrate in a capacitor element formation region, thereby to form the upper electrode including the polysilicon film in the trenches.

公开(公告)号：US20140252441A1

公开(公告)日：2014-09-11

申请号：US14287862

申请日：2014-05-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi HACHISUKA ,  Atsushi AMO ,  Tatsuo KASAOKA ,  Shunji KUBO

IPC: H01L27/108

CPC classification number: H01L27/10829 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/485 ,  H01L27/10811 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate, and insulating layer on the semiconductor substrate, a plurality of contact plugs in the insulating layer, and an insulating layer where capacitors, a plurality of contact plugs, barrier metal layers and copper interconnections are formed. Source/drain regions in the upper surface of the semiconductor substrate are electrically connected to the copper interconnections. One of adjacent source/drain regions in the upper surface of the semiconductor substrate is electrically connected to the copper interconnection, while the other is electrically connected to the capacitor.

Abstract translation: 提供了一种用于提高存储器和逻辑器件的半导体器件的性能的技术。 半导体器件包括半导体衬底和半导体衬底上的绝缘层，绝缘层中的多个接触插塞以及形成电容器，多个接触插塞，阻挡金属层和铜互连的绝缘层。 半导体衬底的上表面中的源/漏区电连接到铜互连。 在半导体衬底的上表面中的相邻源极/漏极区域中的一个电连接到铜互连，而另一个电连接到电容器。

公开(公告)号：US20210036132A1

公开(公告)日：2021-02-04

申请号：US16928854

申请日：2020-07-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi AMO

IPC: H01L29/66 ,  H01L21/28

Abstract: A trench is formed by removing a portion of each of the charge accumulation film and the insulating film located between the control gate electrode and the memory gate electrode. The insulating film is formed in the trench so that the upper surface of each of the insulating film and the charge accumulation film is covered with the insulating film. When exposing the upper surface of the control gate electrode and the memory gate electrode, the upper surface of each of the insulating film and the charge accumulation film is not exposed.

公开(公告)号：US20160268445A1

公开(公告)日：2016-09-15

申请号：US15011510

申请日：2016-01-30

Applicant: Renesas Electronics Corporation

Inventor： Atsushi AMO

IPC: H01L29/792 ,  H01L29/94 ,  H01L29/66

CPC classification number: H01L29/945 ,  G11C16/0466 ,  H01L27/0629 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66181 ,  H01L29/66833 ,  H01L29/792

Abstract: In a semiconductor device including a split gate type MONOS memory, and a trench capacitor element having an upper electrode partially embedded in trenches formed in the main surface of a semiconductor substrate, merged therein, the flatness of the top surface of the upper electrode embedded in the trench is improved. The polysilicon film formed over the semiconductor substrate to form a control gate electrode forming a memory cell of the MONOS memory is embedded in the trenches formed in the main surface of the semiconductor substrate in a capacitor element formation region, thereby to form the upper electrode including the polysilicon film in the trenches.

Abstract translation: 在包括分离栅型MONOS存储器的半导体器件和沟槽电容器元件中，其上部电极部分地嵌入形成在半导体衬底的主表面中的沟槽中，并入其中，上电极的顶表面的平坦度嵌入 沟渠得到改善。 形成在半导体衬底上以形成形成MONOS存储器的存储单元的控制栅电极的多晶硅膜被嵌入形成在电容器元件形成区域中的半导体衬底的主表面中的沟槽中，从而形成上电极，包括 沟槽中的多晶硅膜。