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    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    1.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20160118394A1

    公开(公告)日：2016-04-28

    申请号：US14989999

    申请日：2016-01-07

    Applicant: Renesas Electronics Corporation

    Inventor： Koichi TOBA ,  Hiraku CHAKIHARA ,  Yoshiyuki KAWASHIMA ,  Kentaro SAITO ,  Takashi HASHIMOTO

    IPC: H01L27/115 ,  H01L27/092 ,  H01L21/8234

    CPC classification number: H01L29/7847 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3105 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833

    Abstract: To improve a semiconductor device having a nonvolatile memory. A first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

    Abstract translation: 改善具有非易失性存储器的半导体器件。 形成第一MISFET，第二MISFET和存储单元，并在其上形成由氧化硅膜制成的阻挡膜。 然后，在阻挡膜上形成由氮化硅膜构成的应力施加膜，除去第二MISFET和存储单元上的应力施加膜。 此后，进行热处理以向第一MISFET施加应力。 因此，SMT不应用于每个元件，而是被选择性地应用。 这可以降低由于形成应力施加膜的氮化硅膜中的H（氢）导致的第二MISFET的劣化程度。 这也可以由于形成应力施加膜的氮化硅膜中的H（氢）而降低存储单元的特性的劣化程度。

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    3.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20140242796A1

    公开(公告)日：2014-08-28

    申请号：US14079120

    申请日：2013-11-13

    Applicant: Renesas Electronics Corporation

    Inventor： Koichi TOBA ,  Hiraku CHAKIHARA ,  Yoshiyuki KAWASHIMA ,  Kentaro SAITO ,  Takashi HASHIMOTO

    IPC: H01L21/3105 ,  H01L27/105 ,  H01L21/8234

    CPC classification number: H01L29/7847 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3105 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833

    Abstract: To improve a semiconductor device having a nonvolatile memory. a first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

    Abstract translation: 改善具有非易失性存储器的半导体器件。 形成第一MISFET，第二MISFET和存储单元，并在其上形成由氧化硅膜制成的阻挡膜。 然后，在阻挡膜上形成由氮化硅膜构成的应力施加膜，除去第二MISFET和存储单元上的应力施加膜。 此后，进行热处理以向第一MISFET施加应力。 因此，SMT不应用于每个元件，而是被选择性地应用。 这可以降低由于形成应力施加膜的氮化硅膜中的H（氢）导致的第二MISFET的劣化程度。 这也可以由于形成应力施加膜的氮化硅膜中的H（氢）而降低存储单元的特性的劣化程度。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 审中-公开
    半导体器件的半导体器件和制造方法

    公开(公告)号：US20140209996A1

    公开(公告)日：2014-07-31

    申请号：US14242500

    申请日：2014-04-01

    Applicant: Renesas Electronics Corporation

    Inventor： Koichi TOBA ,  Yasushi ISHII ,  Hiraku CHAKIHARA ,  Kota FUNAYAMA ,  Yoshiyuki KAWASHIMA ,  Takashi HASHIMOTO

    IPC: H01L29/792

    CPC classification number: H01L27/11568 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/792

    Abstract: A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.

    Abstract translation: 提供了具有非易失性存储器的半导体器件，其具有改进的特性。 半导体器件包括控制栅极电极，与控制栅电极相邻设置的存储栅电极，第一绝缘膜和包括电荷存储部分的第二绝缘膜。 在这些部件中，存储栅电极由包括位于第二绝缘膜上的第一硅区的硅膜和位于第一硅区之上的第二硅区构成。 第二硅区域含有p型杂质，第一硅区域的p型杂质浓度低于第二硅区域的p型杂质浓度。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME
    8.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME 有权
    半导体集成电路器件及其制造方法

    公开(公告)号：US20150279788A1

    公开(公告)日：2015-10-01

    申请号：US14739818

    申请日：2015-06-15

    Applicant: Renesas Electronics Corporation

    Inventor： Hiroyuki UCHIYAMA ,  Hiraku CHAKIHARA ,  Teruhisa ICHISE ,  Michimoto KAMINAGA

    IPC: H01L23/544 ,  H01L23/58 ,  H01L27/02 ,  H01L29/78

    CPC classification number: H01L23/544 ,  G03F9/7076 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/76229 ,  H01L21/76819 ,  H01L21/78 ,  H01L22/34 ,  H01L23/585 ,  H01L27/0207 ,  H01L29/78 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor substrate includes scribe and product regions, with grooves formed in the scribe region. The grooves are embedded with an insulating film to provide an isolation region, and an active region, including semiconductor elements, is formed in the product region. Dummy patterns are formed in the scribe region, which include a first dummy pattern and second dummy patterns for preventing dishing of the insulating film. The second dummy patterns are surrounded and defined by the isolation region. A target pattern for optical pattern recognition is arranged over the first dummy pattern, and includes a first conductive film. A plane area of the first dummy pattern is larger than a plane area of each of the second dummy patterns, and the first dummy pattern and the second dummy patterns are arranged in order from an edge of the semiconductor substrate toward the product region.

    Abstract translation: 半导体衬底包括划线和产品区域，在刻划区域中形成有沟槽。 凹槽嵌入绝缘膜以提供隔离区域，并且在产品区域中形成包括半导体元件的有源区域。 在划线区域中形成有虚拟图案，其包括第一虚设图案和用于防止绝缘膜的凹陷的第二虚设图案。 第二虚拟图案由隔离区域包围和限定。 用于光学图案识别的目标图案被布置在第一虚设图案之上，并且包括第一导电膜。 第一虚设图形的平面区域大于第二虚设图案的平面面积，第一虚设图案和第二虚设图案从半导体衬底的边缘朝向产品区域的顺序排列。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    9.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240081068A1

    公开(公告)日：2024-03-07

    申请号：US18344413

    申请日：2023-06-29

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Akio ONO ,  Hiraku CHAKIHARA

    IPC: H10B43/30

    CPC classification number: H10B43/30

    Abstract: A control gate electrode is formed on a semiconductor substrate via a first gate dielectric film. A second gate dielectric film including a charge storage layer is formed on an upper surface of the semiconductor substrate and on one side surface of the control gate electrode. A memory gate electrode is formed on the second gate dielectric film. A cap film formed of a dielectric material is formed on an upper surface of the control gate electrode, and a silicide film is formed on an upper surface of the memory gate electrode. An upper surface of the cap film and an upper surface of the silicide film are exposed from a sidewall spacer SW and an interlayer dielectric film.

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME
    10.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME 有权
    半导体集成电路器件及其制造方法

    公开(公告)号：US20140045320A1

    公开(公告)日：2014-02-13

    申请号：US14059873

    申请日：2013-10-22

    Applicant: Renesas Electronics Corporation

    Inventor： Hiroyuki UCHIYAMA ,  Hiraku CHAKIHARA ,  Teruhisa ICHISE ,  Michimoto KAMINAGA

    IPC: H01L21/306 ,  H01L21/78

    CPC classification number: H01L23/544 ,  G03F9/7076 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/76229 ,  H01L21/76819 ,  H01L21/78 ,  H01L22/34 ,  H01L23/585 ,  H01L27/0207 ,  H01L29/78 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming a semiconductor IC includes forming grooves in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area.

    Abstract translation: 形成半导体IC的方法包括在基板上形成槽，以限定形成在划刻区域的第一虚拟区域和第二虚拟区域，以及形成在产品区域的第三虚拟区域和第四虚拟区域。 第一虚拟区域的宽度大于第二和第三虚拟区域中的每一个的宽度，并且第四虚拟区域的宽度大于每个第三虚拟区域的宽度。 在第一虚拟区域上形成用于光学图案识别的导体图案。 第一虚拟区域形成在导体图案下方，使得沟槽不形成在导体图案之下。 第二虚拟区域在划刻区域处以预定间隔彼此间隔开，并且第三虚拟区域在产品区域处彼此间隔开预定间隔。

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