公开(公告)号：US20190206789A1

公开(公告)日：2019-07-04

申请号：US16192521

申请日：2018-11-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Teruhiro KUWAJIMA ,  Yasutaka NAKASHIBA ,  Akira MATSUMOTO ,  Akio ONO ,  Tetsuya IIDA

IPC: H01L23/522 ,  H01L49/02 ,  H01L29/93 ,  H01L27/06 ,  H03L7/099

CPC classification number: H01L23/5223 ,  H01L27/0629 ,  H01L28/86 ,  H01L29/93 ,  H03L7/099

Abstract: A semiconductor device has a coil and wirings under the coil. In addition, a distance between the upper face of the wirings and the bottom face of the cod is 7 μm or larger, and the wirings have a plurality of linear wiring parts each wiring width of which is 1 μm or smaller. In addition, the linear wiring parts do not configure a loop wiring, and the coil and the linear wiring parts are overlapped with each other in planar view. Even if such wirings (linear wiring parts) are arranged under the coil, the characteristics (for example, RF characteristics) of the semiconductor device are not deteriorated. In addition, the area of the semiconductor device can be reduced or high integration of elements can be realized by laminating elements (for example, MOM capacitance elements and the like) having the coil and the linear wiring parts.

公开(公告)号：US20240081068A1

公开(公告)日：2024-03-07

申请号：US18344413

申请日：2023-06-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Akio ONO ,  Hiraku CHAKIHARA

IPC: H10B43/30

CPC classification number: H10B43/30

Abstract: A control gate electrode is formed on a semiconductor substrate via a first gate dielectric film. A second gate dielectric film including a charge storage layer is formed on an upper surface of the semiconductor substrate and on one side surface of the control gate electrode. A memory gate electrode is formed on the second gate dielectric film. A cap film formed of a dielectric material is formed on an upper surface of the control gate electrode, and a silicide film is formed on an upper surface of the memory gate electrode. An upper surface of the cap film and an upper surface of the silicide film are exposed from a sidewall spacer SW and an interlayer dielectric film.

公开(公告)号：US20200168545A1

公开(公告)日：2020-05-28

申请号：US16653127

申请日：2019-10-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi UCHIDA ,  Akio ONO ,  Shinichi KUWABARA ,  Yasutaka NAKASHIBA

IPC: H01L23/522 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

Abstract: A first semiconductor chip and a second semiconductor chip are stacked such that a first inductor and a second inductor face each other. An insulating sheet is disposed between the first semiconductor chip and the second semiconductor chip. The sealing member seals the first semiconductor chip, the second semiconductor chip, and the insulating sheet. The sealing member is disposed both between the insulating sheet and the first semiconductor chip and between the insulating sheet and the second semiconductor chip.

公开(公告)号：US20230093724A1

公开(公告)日：2023-03-23

申请号：US17876067

申请日：2022-07-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi AMO ,  Hiraku CHAKIHARA ,  Hiroshi YANAGITA ,  Akio ONO

IPC: H01L21/66 ,  H01L27/11 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51

Abstract: A method of manufacturing a semiconductor device capable of detecting occurrence of a Hi-K disappearance is provided. The method of manufacturing a semiconductor device includes a step of manufacturing a test pattern including a reference resistance, a gate leakage resistance through which a gate leakage current flows and connected in series with the reference resistance, and a step of measuring a change in voltage at a connection node between the reference resistance and the gate leakage resistance caused by the flow of the gate leakage current.