公开(公告)号：US20140252441A1

公开(公告)日：2014-09-11

申请号：US14287862

申请日：2014-05-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi HACHISUKA ,  Atsushi AMO ,  Tatsuo KASAOKA ,  Shunji KUBO

IPC: H01L27/108

CPC classification number: H01L27/10829 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/485 ,  H01L27/10811 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate, and insulating layer on the semiconductor substrate, a plurality of contact plugs in the insulating layer, and an insulating layer where capacitors, a plurality of contact plugs, barrier metal layers and copper interconnections are formed. Source/drain regions in the upper surface of the semiconductor substrate are electrically connected to the copper interconnections. One of adjacent source/drain regions in the upper surface of the semiconductor substrate is electrically connected to the copper interconnection, while the other is electrically connected to the capacitor.

Abstract translation: 提供了一种用于提高存储器和逻辑器件的半导体器件的性能的技术。 半导体器件包括半导体衬底和半导体衬底上的绝缘层，绝缘层中的多个接触插塞以及形成电容器，多个接触插塞，阻挡金属层和铜互连的绝缘层。 半导体衬底的上表面中的源/漏区电连接到铜互连。 在半导体衬底的上表面中的相邻源极/漏极区域中的一个电连接到铜互连，而另一个电连接到电容器。