公开(公告)号：US20200343207A1

公开(公告)日：2020-10-29

申请号：US16927006

申请日：2020-07-13

Applicant: Renesas Electronics Corporation

Inventor： Takashi TONEGAWA

IPC: H01L23/00 ,  H01L23/495 ,  H01L29/78 ,  H01L29/66 ,  H01L23/31 ,  H01L23/433

Abstract: A method of manufacturing a semiconductor device includes forming an interlayer insulating film over a main surface of a semiconductor substrate, forming a first conductive film pattern for a first pad and a second conductive film pattern for a second pad over the interlayer insulating film, forming an insulating film over the interlayer insulating film such that the insulating film covers the first and the second conductive film patterns, forming a first opening portion for the first pad, the first opening portion exposing a portion of the first conductive film pattern, and a second opening portion for the second pad, the second opening portion exposing a portion of the second conductive film pattern, in the insulating film, and forming a first plated layer by plating over the portion of the first conductive film pattern exposed in the first opening portion, and a second plated layer.

公开(公告)号：US20180138136A1

公开(公告)日：2018-05-17

申请号：US15788637

申请日：2017-10-19

Applicant: Renesas Electronics Corporation

Inventor： Takashi TONEGAWA

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L24/05 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/4334 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/562 ,  H01L24/03 ,  H01L24/06 ,  H01L24/32 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2224/03464 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05017 ,  H01L2224/05019 ,  H01L2224/05025 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05096 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/32245 ,  H01L2224/40151 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/49173 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/84801 ,  H01L2924/13055 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014

Abstract: An insulating film is formed such that the insulating film covers a source electrode and a gate electrode, and an opening portion exposing a portion of the source electrode and an opening portion exposing a portion of the gate electrode are formed in the insulating film. A plated layer is formed over the source electrode exposed in the opening portion, and a plated layer is formed over the gate electrode exposed in the opening portion. A source pad is formed of the portion of the source electrode exposed in the opening portion, and the plated layer, and a gate pad is formed of the portion of the gate electrode exposed in the opening portion, and the plated layer. An area of the opening portion for the gate pad is smaller than an area of the opening portion for the source pad, and a thickness of the plated layer over the gate electrode is greater than a thickness of the plated layer over the source electrode.

公开(公告)号：US20230111921A1

公开(公告)日：2023-04-13

申请号：US17885955

申请日：2022-08-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takashi TONEGAWA

IPC: H01L23/00 ,  H01L29/40 ,  H01L29/417 ,  G01R31/26

Abstract: First conductive layer is connected to an impurity region which is a source region or an emitter region. A first conductive layer having an emitter pad and a second conductive layer having a Kelvin emitter pad and a relay pad are separated. A plane occupied area of the Kelvin emitter pad is smaller than a plane occupied area of the emitter pad.

公开(公告)号：US20240162343A1

公开(公告)日：2024-05-16

申请号：US18452805

申请日：2023-08-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuji ENARI ,  Takashi TONEGAWA

IPC: H01L29/78 ,  H01L23/00 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7802 ,  H01L24/05 ,  H01L24/06 ,  H01L29/1095 ,  H01L29/66712 ,  H01L2224/05017 ,  H01L2224/05022 ,  H01L2224/05082 ,  H01L2224/05557 ,  H01L2224/05561 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2924/13091

Abstract: An interlayer insulating film is formed on an upper surface of a semiconductor substrate. A source pad and a kelvin pad, a gate pad, and a drain pad each having a smaller plane area than a plane area of the source pad are formed on the interlayer insulating film. A first plating layer is formed on the source pad. A second plating layer is formed on each of the kelvin pad, the gate pad, and the drain pad. A material of an uppermost surface of the first plating layer is a metal other than a noble metal, and a material of an uppermost surface of the second plating layer is a noble metal.

公开(公告)号：US20230411323A1

公开(公告)日：2023-12-21

申请号：US18188781

申请日：2023-03-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Etsuko WATANABE ,  Takashi TONEGAWA

IPC: H01L23/00

CPC classification number: H01L24/06 ,  H01L23/49513 ,  H01L24/40 ,  H01L24/48 ,  H01L24/05 ,  H01L24/73 ,  H01L24/03 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/06505 ,  H01L2224/06102 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2924/0132 ,  H01L2224/05186 ,  H01L2924/04941 ,  H01L2224/05124 ,  H01L2224/05138 ,  H01L2924/01014 ,  H01L2224/05147 ,  H01L2924/0133 ,  H01L2224/05155 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05644 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05118 ,  H01L2224/05567 ,  H01L2224/03464 ,  H01L2224/48245 ,  H01L2224/48091 ,  H01L2224/37147 ,  H01L2224/37139 ,  H01L2224/40245 ,  H01L24/29 ,  H01L2224/29139 ,  H01L24/32 ,  H01L2224/32245 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/73263 ,  H01L24/37

Abstract: A dielectric layer has a first opening exposing a surface of a first conductive layer and a second opening exposing a surface of a second conductive layer and having an opening area smaller than an opening area of the first opening. A material of the surface of the second conductive layer exposed from the second opening is different from a material of the surface of the first conductive layer exposed from the first opening, and includes aluminum.

公开(公告)号：US20170092605A1

公开(公告)日：2017-03-30

申请号：US15217983

申请日：2016-07-23

Applicant: Renesas Electronics Corporation

Inventor： Takashi TONEGAWA

IPC: H01L23/00

CPC classification number: H01L23/5283 ,  H01L21/31 ,  H01L21/31056 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/44 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/4827 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/84 ,  H01L24/85 ,  H01L29/1095 ,  H01L29/417 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813 ,  H01L2224/02126 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/02206 ,  H01L2224/02215 ,  H01L2224/031 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/03522 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05017 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48799 ,  H01L2224/48844 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/85045 ,  H01L2224/85181 ,  H01L2224/85203 ,  H01L2924/05042 ,  H01L2924/0509 ,  H01L2924/05442 ,  H01L2924/07025 ,  H01L2924/1203 ,  H01L2924/1206 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/00013 ,  H01L2924/059 ,  H01L2924/0103 ,  H01L2924/00

Abstract: Properties of a semiconductor device are improved. A semiconductor device is configured so as to have a protective film provided over an interconnection and having an opening, and a plating film provided in the opening. A slit is provided in a side face of the opening, and the plating film is also disposed in the slit. Thus, the slit is provided in the side face of the opening, and the plating film is also grown in the slit. This results in a long penetration path of a plating solution during subsequent formation of the plating film. Hence, a corroded portion is less likely to be formed in the interconnection (pad region). Even if the corroded portion is formed, a portion of the slit is corroded prior to the interconnection (pad region) at a sacrifice, making it possible to suppress expansion of the corroded portion into the interconnection (pad region).

公开(公告)号：US20160284980A1

公开(公告)日：2016-09-29

申请号：US15060820

申请日：2016-03-04

Applicant: Renesas Electronics Corporation

Inventor： Takashi TONEGAWA ,  Keiji SAKAMOTO

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/08

CPC classification number: H01L43/02 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

Abstract: An object is to prevent a short failure in magnetic tunnel junction and thereby suppress a semiconductor device having a magnetic memory cell from having deteriorated reliability. First, a data reference layer and a cap layer are patterned. After formation of an oxygen-free first insulating film on their side walls, a base layer, a data recording layer, and a tunnel barrier layer are patterned. During patterning of the base layer, data recording layer, and tunnel barrier layer, adhesion of a metal substance of the data reference layer and the cap layer to the side wall of the tunnel barrier layer can be prevented because the data reference layer and the cap layer are covered by the first insulating film.

Abstract translation: 本发明的目的是防止磁性隧道结中的短路故障，从而抑制具有磁存储单元的半导体器件的可靠性降低。 首先，对数据参考层和盖层进行图案化。 在其侧壁上形成无氧的第一绝缘膜之后，对基底层，数据记录层和隧道势垒层进行图案化。 在图案化基底层，数据记录层和隧道势垒层时，可以防止数据参考层和覆盖层与隧道势垒层的侧壁的粘附，因为数据参考层和盖 层被第一绝缘膜覆盖。

公开(公告)号：US20240170421A1

公开(公告)日：2024-05-23

申请号：US18484982

申请日：2023-10-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Teruhiro KUWAJIMA ,  Tohru KAWAI ,  Takashi TONEGAWA

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/06 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/0391 ,  H01L2224/05005 ,  H01L2224/05011 ,  H01L2224/05013 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05138 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05553 ,  H01L2224/05562 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/06135 ,  H01L2924/01014 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/04941

Abstract: A pad is formed on an interlayer insulation film, a first insulation film is formed on the interlayer insulation film so as to cover the pad, and a second insulation film is formed on the first insulation film so as to cover the pad. The first insulation film includes a first opening partially exposing the pad, and the second insulation film includes a second opening partially exposing the pad, and the second opening is included in the first opening in plan view. The first insulation film is made of silicon oxide, and the second insulation film is made of silicon nitride or silicon oxynitride. A nickel plating film is formed on the pad exposed from the second opening. A distance from an outer circumference of the pad to an inner wall of the first opening increases in accordance with a thickness of the nickel plating film.

公开(公告)号：US20210225789A1

公开(公告)日：2021-07-22

申请号：US17225639

申请日：2021-04-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takashi TONEGAWA ,  Hiroshi INAGAWA

IPC: H01L23/00 ,  H01L29/04 ,  H01L29/78 ,  H01L29/66 ,  H01L29/861 ,  H01L29/45 ,  H01L23/495

Abstract: To improve reliability of a semiconductor device. There are provided the semiconductor device and a method of manufacturing the same, the semiconductor including a pad electrode that is formed over a semiconductor substrate and includes a first conductive film and a second conductive film formed over the first conductive film, and a plating film that is formed over the second conductive film and used to be coupled to an external connection terminal (TR). The first conductive film and the second conductive film contains mainly aluminum. The crystal surface on the surface of the first conductive film is different from the crystal surface on the surface of the second conductive film.

公开(公告)号：US20190006300A1

公开(公告)日：2019-01-03

申请号：US15988483

申请日：2018-05-24

Applicant: Renesas Electronics Corporation

Inventor： Takashi MORIYAMA ,  Takashi TONEGAWA

IPC: H01L23/00 ,  H01L23/522

Abstract: A semiconductor device and a method for manufacturing the semiconductor device which ensure improved reliability, permit further miniaturization, and suppress the increase in manufacturing cost. The semiconductor device includes: a pad electrode formed in the uppermost wiring layer of a multilayer wiring layer formed over a semiconductor substrate; a surface protective film formed in a manner to cover the pad electrode; an opening made in the surface protective film in a manner to expose the pad electrode partially; and a conductive layer formed over the pad electrode exposed at the bottom of the opening. The thickness of the conductive layer formed over the pad electrode is smaller than the thickness of the surface protective film formed over the pad electrode.