公开(公告)号：US20210005230A1

公开(公告)日：2021-01-07

申请号：US16706429

申请日：2019-12-06

Applicant: QUALCOMM Incorporated

Inventor： Zhongze WANG ,  Xia LI ,  Ye LU ,  Yandong GAO

IPC: G11C7/06 ,  G11C7/10 ,  G11C11/4094 ,  G11C11/419 ,  G11C11/4074 ,  G06N3/06

Abstract: A charge sharing Compute In Memory (CIM) may comprise an XNOR bit cell with an internal capacitor between the XNOR output node and a system voltage. Alternatively, a charge sharing CIM may comprise an XNOR bit cell with an internal capacitor between the XNOR output node and a read bit line. Alternatively, a charge sharing CIM may comprise an XNOR bit cell with an internal cap between XNOR and read bit line with a separate write bit line and write bit line bar.

公开(公告)号：US20200075582A1

公开(公告)日：2020-03-05

申请号：US16115206

申请日：2018-08-28

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Chao SONG ,  Haitao CHENG

IPC: H01L27/06 ,  H01L27/02 ,  H01L23/522 ,  H01L49/02

Abstract: A resistor-capacitor (RC) delay circuit includes a first capacitor at a first level, a resistor at a second level and a second capacitor at a third level. The second capacitor is electrically connected in parallel with the first capacitor. The second capacitor has a footprint within a footprint of the first capacitor. The resistor is coupled in shunt with the first capacitor and the second capacitor.

公开(公告)号：US20200035674A1

公开(公告)日：2020-01-30

申请号：US16277751

申请日：2019-02-15

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Haining YANG

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8234

Abstract: A fin field effect transistors (FinFET) array includes a first transistor having a fin and a first conductive gate on the fin. The FinFET array also includes a second transistor having another fin and a second conductive gate on the other fin. The FinFET array further includes a first dielectric material and a self-aligned dielectric spacer. The first dielectric material is between the first transistor and the second transistor and on at least a portion of sidewalls of each of the first conductive gate and the second conductive gate. The self-aligned dielectric spacer is on at least a portion of the sidewalls of each of the first conductive gate and the second conductive gate.

公开(公告)号：US20190221645A1

公开(公告)日：2019-07-18

申请号：US16288558

申请日：2019-02-28

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Junjing BAO ,  Bin YANG ,  Lixin GE ,  Yun YUE

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/72 ,  H01L29/10

CPC classification number: H01L29/1606 ,  H01L21/02115 ,  H01L21/02181 ,  H01L21/02271 ,  H01L29/1004 ,  H01L29/1608 ,  H01L29/66037 ,  H01L29/66068 ,  H01L29/6656 ,  H01L29/72 ,  H01L29/785

Abstract: An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.

公开(公告)号：US20220108983A1

公开(公告)日：2022-04-07

申请号：US17061941

申请日：2020-10-02

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Ye LU ,  Chenjie TANG ,  Peijie FENG

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78

Abstract: Certain aspects of the present disclosure relate to a semiconductor device (e.g., a gate-all-around (GAA) semiconductor device) comprising at least one superlattice fin. One example superlattice fin includes a first plurality of nanosheets composed of a first semiconductor material and a second plurality of nanosheets composed of a second semiconductor material, the second semiconductor material being different from the first semiconductor material, wherein a width of a first nanosheet in the first plurality of nanosheets differs from a width of a second nanosheet in the second plurality of nanosheets, the second nanosheet being adjacent to the first nanosheet.

公开(公告)号：US20210143050A1

公开(公告)日：2021-05-13

申请号：US16676663

申请日：2019-11-07

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Ye LU ,  Haitao CHENG

IPC: H01L21/764 ,  H01L29/06 ,  H01L49/02

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device including an air gap underneath passive devices. The semiconductor device generally includes a substrate layer, a passive device layer, and a dielectric layer disposed between the substrate layer and the passive device layer, wherein the dielectric layer includes an air gap disposed beneath at least one passive device in the passive device layer.

公开(公告)号：US20200066858A1

公开(公告)日：2020-02-27

申请号：US16112484

申请日：2018-08-24

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Peijie FENG ,  Ye LU ,  Bin YANG

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/51 ,  H01L29/66

Abstract: A thin film transistor may include an insulating substrate and a layer of semiconductor material disposed over the insulating substrate. The thin film transistor may further include a gate electrode, a source electrode and a drain electrode disposed over the insulating substrate. The thin film transistor may further include a layer of first dielectric material disposed in between the gate electrode and the source and drain electrodes, and a layer of second dielectric material in contact with the layer of first dielectric material. The second dielectric material has a negative index.

公开(公告)号：US20200043863A1

公开(公告)日：2020-02-06

申请号：US16051525

申请日：2018-08-01

Applicant: QUALCOMM Incorporated

Inventor： Haitao CHENG ,  Ye LU ,  Chao SONG

IPC: H01L23/552 ,  H01L23/66

Abstract: Aspects generally relate to tuning a guard ring in an integrated circuit. A guard ring with a gap surrounds a circuit. The level of isolation provided by the guard ring at a particular frequency can be adjusted by coupling a tuning circuit cross the gap of the guard ring. If the circuit in the guard ring is an inductive circuit the level of inductance at a particular frequency can be adjusted by selecting the appropriate tuning circuit across the gap of the guard ring.

公开(公告)号：US20180366592A1

公开(公告)日：2018-12-20

申请号：US15686827

申请日：2017-08-25

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Yun YUE ,  Chuan-Hsing CHEN ,  Bin YANG ,  Lixin GE ,  Ken LIAO

IPC: H01L29/93 ,  H01L29/66 ,  H01L29/423 ,  H01L29/45

CPC classification number: H01L29/93 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/66 ,  H01L29/4232 ,  H01L29/456 ,  H01L29/66174 ,  H01L29/66181

Abstract: A short-channel metal oxide semiconductor varactor may include a source region of a first polarity having a source via contact. The varactor may further include a drain region of the first polarity having a drain via contact. The varactor may further include a channel region of the first polarity between the source region and the drain region. The channel region may include a gate. The varactor may further include at least one self-aligned contact (SAC) on the gate and between the source via contact and the drain via contact.

公开(公告)号：US20180342513A1

公开(公告)日：2018-11-29

申请号：US15663602

申请日：2017-07-28

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Junjing BAO ,  Bin YANG ,  Lixin GE ,  Yun YUE

IPC: H01L27/092 ,  H01L29/04 ,  H01L21/78 ,  H01L29/16 ,  H01L29/423 ,  H01L29/49 ,  H01L29/06 ,  H01L21/8238

Abstract: A complementary metal-oxide-semiconductor (CMOS) transistor may include a first semiconductor structure and a gate stack on the first semiconductor structure. The gate stack may include a gate dielectric layer on the first semiconductor structure, a work function material on the gate dielectric layer, and a gate metal fill material on the work function material of the gate stack. The gate metal fill material may include a low resistivity carbon alloy. A dielectric fill material may be included on the gate stack.