公开(公告)号：US10290352B2

公开(公告)日：2019-05-14

申请号：US14633793

申请日：2015-02-27

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Xiao Lu ,  Xiaonan Chen ,  Zhongze Wang

IPC: G11C16/10 ,  H01L29/792 ,  G11C16/04 ,  G11C17/16 ,  G11C17/18 ,  H01L29/423 ,  H01L27/112 ,  G11C17/14

Abstract: A semiconductor device for a one-time programmable (OTP) memory according to some examples of the disclosure includes a gate, a dielectric region below the gate, a source terminal below the dielectric region and offset to one side, a drain terminal below the dielectric region and offset to an opposite side from the source terminal, a drain side charge trap in the dielectric region capable of programming the semiconductor device, and a source side charge trap in the dielectric region opposite the drain side charge trap and capable of programming the semiconductor device.

公开(公告)号：US20180158935A1

公开(公告)日：2018-06-07

申请号：US15371512

申请日：2016-12-07

Applicant: QUALCOMM Incorporated

Inventor： Hao Wang ,  Haining Yang ,  Xiaonan Chen

IPC: H01L29/739 ,  H01L27/02 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7391 ,  H01L27/0255 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/495 ,  H01L29/66356 ,  H01L29/7851

Abstract: Asymmetric gated fin field effect transistor (FET) (finFET) diodes are disclosed. In one aspect, an asymmetric gated finFET diode employs a substrate that includes a well region of a first-type and a fin disposed in a direction. A first source/drain region is employed that includes a first-type doped material disposed in the fin having a first length in the direction. A second source/drain region having a second length in the direction larger than the first length is employed that includes a second-type doped material disposed in the fin. A gate region is disposed between the first source/drain region and the second source/drain region and has a third length in the direction that is larger than the first length and larger than the second length. The wider gate region increases a length of a depletion region of the asymmetric gated finFET diode, which reduces current leakage while avoiding increase in area.

公开(公告)号：US09812188B2

公开(公告)日：2017-11-07

申请号：US14631603

申请日：2015-02-25

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Zhongze Wang ,  Xiaonan Chen ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/20 ,  G11C11/417 ,  G11C29/02 ,  G11C29/24 ,  G11C29/50 ,  G11C29/04

CPC classification number: G11C11/419 ,  G11C7/20 ,  G11C11/417 ,  G11C29/021 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/0407 ,  G11C2029/0409 ,  G11C2029/5002

Abstract: An apparatus includes a static random-access memory and circuitry configured to initiate a corrective action associated with the static random-access memory. The corrective action may be initiated based on a number of static random-access memory cells that have a particular state responsive to a power-up of the static random-access memory.

公开(公告)号：US09449709B1

公开(公告)日：2016-09-20

申请号：US14863417

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Xiaonan Chen ,  Niladri Narayan Mojumder ,  Zhongze Wang ,  Weidan Li

IPC: G11C11/00 ,  G11C17/18 ,  G11C11/419 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C7/02 ,  G11C11/4125 ,  G11C11/419 ,  G11C17/146

Abstract: A volatile and one-time program (OTP) compatible asymmetric memory cell may include a first pull-up transistor having a first threshold voltage. The asymmetric memory cell may also include a second pull-up transistor having a second threshold voltage that differs from the first threshold voltage. The asymmetric memory cell may further include a switch coupled to a well of the first pull-up transistor and the second pull-up transistor to alternate between a program voltage (Vpg) and a power supply voltage. The asymmetric memory cell may also include a peripheral switching circuit to control programming of the asymmetric memory cell.

Abstract translation: 易失性和一次性程序（OTP）兼容非对称存储单元可以包括具有第一阈值电压的第一上拉晶体管。 非对称存储单元还可以包括具有不同于第一阈值电压的第二阈值电压的第二上拉晶体管。 非对称存储单元还可以包括耦合到第一上拉晶体管和第二上拉晶体管的阱的开关，以在编程电压（Vpg）和电源电压之间交替。 非对称存储单元还可以包括用于控制非对称存储单元的编程的外围开关电路。

公开(公告)号：US09245648B1

公开(公告)日：2016-01-26

申请号：US14498519

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Xiaonan Chen ,  Xiao Lu

IPC: G11C17/00 ,  G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C11/5692 ,  G11C17/16

Abstract: In a one-time-programming (OTP) memory cell, dual-voltage sensing is utilized to determine whether the memory cell has experienced a non/soft breakdown or a hard breakdown. The drain current of the memory cell is read when the gate voltage is at a first predetermined voltage, and if the read drain current is greater than a predetermined current level, then a hard breakdown is detected. One or more additional readings of the current may be obtained to determine that a hard breakdown has occurred. If the read drain current is less than the predetermined current level, then a non/soft breakdown is detected. The threshold voltage of the memory cell may be shifted, and a second reading of the drain current may be obtained when the gate voltage is at a second predetermined voltage in case the memory cell experiences a non/soft breakdown.

Abstract translation: 在一次编程（OTP）存储器单元中，利用双电压感测来确定存储器单元是否经历了非/软故障或硬故障。 当栅极电压处于第一预定电压时，读取存储单元的漏极电流，并且如果读取的漏极电流大于预定电流电平，则检测到硬故障。 可以获得电流的一个或多个附加读数以确定发生了硬故障。 如果读漏极电流小于预定电流电平，则检测到非/软击穿。 当存储器单元经历非/软击穿时，当栅极电压处于第二预定电压时，可以移位存储单元的阈值电压，并且可以获得漏极电流的第二读数。

公开(公告)号：US20220392524A1

公开(公告)日：2022-12-08

申请号：US17341797

申请日：2021-06-08

Applicant: QUALCOMM Incorporated

Inventor： Xiaonan Chen ,  Zhongze Wang ,  Yandong Gao ,  Mustafa Badaroglu

IPC: G11C11/419 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/4091 ,  G06N3/063 ,  G06F7/544

Abstract: Digital compute-in-memory (DCIM) bit cell circuit layouts and DCIM array circuits for multiple operations per column are disclosed. A DCIM bit cell array circuit including DCIM bit cell circuits comprising exemplary DCIM bit cell circuit layouts disposed in columns is configured to evaluate the results of multiple multiply operations per clock cycle. The DCIM bit cell circuits in the DCIM bit cell circuit layouts each couples to one of a plurality of column output lines in a column. In this regard, in each cycle of a system clock, each of the plurality of column output lines receives a result of a multiply operation of a DCIM bit cell circuit coupled to the column output line. The DCIM bit cell array circuit includes digital sense amplifiers coupled to each of the plurality of column output lines to reliably evaluate a result of a plurality of multiply operations per cycle.

公开(公告)号：US20220172770A1

公开(公告)日：2022-06-02

申请号：US17404378

申请日：2021-08-17

Applicant: QUALCOMM Incorporated

Inventor： Xiaonan Chen ,  Zhongze Wang

IPC: G11C11/4096 ,  G11C11/4074 ,  G11C11/408 ,  G11C5/06 ,  H03K19/017 ,  H03K19/20

Abstract: Compute-in-memory (CIM) bit cell array circuits include CIM bit cell circuits for multiply-accumulate operations. The CIM bit cell circuits include a memory bit cell circuit for storing a weight data in true and complement form. The CIM bit cell circuits include a true pass-gate circuit and a complement pass-gate circuit for generating a binary product of the weight data and an activation input on a product node. An RWL circuit couples the product node to a ground voltage for initialization. The CIM bit cell circuits also include a plurality of consecutive gates each coupled to at least one of the memory bit cell circuit, the true pass-gate circuit, the complement pass-gate circuit, and the RWL circuit. Each of the CIM bit cell circuits in the CIM bit cell array circuit is disposed in an orientation of a CIM bit cell circuit layout including the RWL circuit.

公开(公告)号：US09876123B2

公开(公告)日：2018-01-23

申请号：US14495507

申请日：2014-09-24

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jeffrey Junhao Xu ,  Xiao Lu ,  Bin Yang ,  Jun Yuan ,  Xiaonan Chen ,  Zhongze Wang

IPC: G11C16/10 ,  H01L29/792 ,  H01L29/423 ,  H01L29/51 ,  G11C17/18 ,  H01L27/112 ,  G11C16/26 ,  G11C16/04

CPC classification number: H01L29/792 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/26 ,  G11C17/18 ,  H01L27/11206 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517

Abstract: An apparatus includes a metal gate, a substrate material, and an oxide layer between the metal gate and the substrate material. The oxide layer includes a hafnium oxide layer contacting the metal gate and a silicon dioxide layer contacting the substrate material and contacting the hafnium oxide layer. The metal gate, the substrate material, and the oxide layer are included in a one-time programmable (OTP) memory device. The OTP memory device includes a transistor. A non-volatile state of the OTP memory device is based on a threshold voltage shift of the OTP memory device.

公开(公告)号：US09496048B2

公开(公告)日：2016-11-15

申请号：US14656699

申请日：2015-03-12

Applicant: QUALCOMM Incorporated

Inventor： Xiaonan Chen ,  Zhongze Wang ,  Xia Li

IPC: G11C17/08

CPC classification number: G11C17/08 ,  G11C7/04 ,  G11C17/12 ,  G11C17/123

Abstract: An OTP memory array includes a plurality of differential P-channel metal oxide semiconductor (PMOS) OTP memory cells programmable and readable in predetermined states of program and read operations, and is capable of providing sufficient margins against global process variations and temperature variations while being compatible with standard logic fin-shaped field effect transistor (FinFET) processes to obviate the need for additional masks and costs associated with additional masks.

Abstract translation: OTP存储器阵列包括在预定的程序和读取操作状态下可编程和可读的多个差分P沟道金属氧化物半导体（PMOS）OTP存储器单元，并且能够在兼容的同时为全局工艺变化和温度变化提供足够的余量 具有标准逻辑鳍状场效应晶体管（FinFET）处理，以避免需要额外的掩模和与附加掩模相关联的成本。

公开(公告)号：US09431097B2

公开(公告)日：2016-08-30

申请号：US14579891

申请日：2014-12-22

Applicant: QUALCOMM Incorporated

Inventor： Xiaonan Chen ,  Zhongze Wang ,  Xia Li

IPC: G11C11/00 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C11/4125 ,  G11C14/0054

Abstract: A method of operation of a static random access memory (SRAM) storage element includes programming a value to the SRAM storage element prior to a power-down event. The method further includes, in response to a power-on event at the SRAM storage element after the power-down event, increasing a supply voltage of the SRAM storage element and sensing a state of the SRAM storage element to determine the value programmed to the SRAM storage element prior to the power-down event. In a particular example, an apparatus includes the SRAM storage element and control circuitry coupled to the SRAM storage element. The control circuitry may be configured to program the value to the SRAM storage element, to increase the supply voltage, and to sense the state of the SRAM storage element to determine the value programmed to the SRAM storage element prior to the power-down event.

Abstract translation: 静态随机存取存储器（SRAM）存储元件的操作方法包括在掉电事件之前将值编程到SRAM存储元件。 该方法还包括响应于在掉电事件之后的SRAM存储元件处的电源接通事件，增加SRAM存储元件的电源电压并感测SRAM存储元件的状态，以确定被编程到 SRAM存储元件在掉电事件之前。 在特定示例中，装置包括耦合到SRAM存储元件的SRAM存储元件和控制电路。 控制电路可以被配置为将值编程到SRAM存储元件，以增加电源电压，并且感测SRAM存储元件的状态以确定在掉电事件之前被编程到SRAM存储元件的值。