公开(公告)号：US20180047687A1

公开(公告)日：2018-02-15

申请号：US15233902

申请日：2016-08-10

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  Jie FU ,  Manuel ALDRETE ,  Jonghae KIM ,  Changhan Hobie YUN ,  David Francis BERDY ,  Chengjie ZUO ,  Mario Francisco VELEZ

IPC: H01L23/00 ,  H01L23/367 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/09 ,  H01L21/563 ,  H01L23/3157 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/14051 ,  H01L2224/14181 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/15321 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor device according to some examples of the disclosure may include a package substrate, a semiconductor die coupled to one side of the package substrate with a first set of contacts on an active side of the semiconductor die and coupled to a plurality of solder prints with a second set of contacts on a back side of the semiconductor die. The semiconductor die may include a plurality of vias connecting the first set of contacts to the second set of contacts and configured to allow heat to be transferred from the active side of the die to the plurality of solder prints for a shorter heat dissipation path.

公开(公告)号：US20150206812A1

公开(公告)日：2015-07-23

申请号：US14263823

申请日：2014-04-28

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan KIM ,  Milind Pravin SHAH ,  Manuel ALDRETE

IPC: H01L23/053 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/3205

CPC classification number: H01L23/053 ,  H01L21/30604 ,  H01L21/32051 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Methods and apparatus for cavity formation in a semiconductor package substrate are provided. In one embodiment, a method for producing at least one cavity within a semiconductor package substrate includes etching the semiconductor package substrate from a surface of the semiconductor package substrate at least one intended cavity location in order to obtain at least one cavity. The method includes depositing a copper portion on a substrate in a cavity location. Next, the method includes masking the substrate while keeping the copper portion exposed. Lastly, the method includes etching the substrate to form a cavity by etching away the copper portion. The structure formed includes a cavity that extends partially through the substrate without damaging a glass fabric embedded in the substrate.

Abstract translation: 提供了半导体封装基板中的空腔形成方法和装置。 在一个实施例中，一种用于在半导体封装衬底内产生至少一个空腔的方法包括从半导体封装衬底的表面至少一个预定的腔位置蚀刻半导体封装衬底，以便获得至少一个空腔。 该方法包括在空腔位置的基板上沉积铜部分。 接下来，该方法包括在保持铜部分暴露的同时掩蔽基板。 最后，该方法包括通过蚀刻掉铜部分来蚀刻基板以形成空腔。 所形成的结构包括部分地延伸穿过基底的空腔，而不会损害嵌入在基底中的玻璃织物。

公开(公告)号：US20250125234A1

公开(公告)日：2025-04-17

申请号：US18486970

申请日：2023-10-13

Applicant: QUALCOMM Incorporated

Inventor： Manuel ALDRETE ,  Rajneesh KUMAR ,  Zhijie WANG ,  Aniket PATIL ,  Srikanth KULKARNI

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10

Abstract: In an aspect, an integrated circuit (IC) package includes a base structure, an IC component disposed on the base structure, a plurality of interposer connection structures disposed on the base structure, and an interposer structure disposed over the IC component and the plurality of interposer connection structures. The plurality of interposer connection structures is configured to connect the base structure and the interposer structure. Each interposer connection structure of the plurality of interposer connection structures includes a bond ball portion that is connected to the base structure, and a bond wire portion that is coupled to the bond ball portion and extends toward the interposer structure. A width of the bond ball portion is greater than a width of the bond wire portion.

公开(公告)号：US20250046688A1

公开(公告)日：2025-02-06

申请号：US18363557

申请日：2023-08-01

Applicant: QUALCOMM Incorporated

Inventor： Zhijie WANG ,  Rajneesh KUMAR ,  Manuel ALDRETE ,  Sang-Jae LEE ,  Seongho KIM

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H10B80/00

Abstract: An integrated device includes a die including active circuitry and a first set of contacts; a first substrate including a second set of contacts and a third set of contacts on a first side of the first substrate and a fourth set of contacts on a second side of the first substrate; a mold compound disposed on the first side of the first substrate and at least partially encapsulating the die; and a set of through mold conductors coupled to the third set of contacts and extending through the mold compound, wherein an upper surface of the mold compound, an upper surface of the die, and an upper surface of each of the set of through mold conductors are coplanar.

公开(公告)号：US20230369230A1

公开(公告)日：2023-11-16

申请号：US17742001

申请日：2022-05-11

Applicant: QUALCOMM Incorporated

Inventor： Yangyang SUN ,  Manuel ALDRETE ,  Lily ZHAO

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L23/5383 ,  H01L24/08 ,  H01L23/3107 ,  H01L23/5384 ,  H01L25/105 ,  H01L25/50 ,  H01L21/56

Abstract: A package comprising a first metallization portion, a first integrated device, an interconnection die, a second metallization portion, and an encapsulation layer. The first metallization portion includes at least one first dielectric layer and a first plurality of metallization interconnects. The first integrated device is coupled to the first metallization portion. The interconnection die is coupled to the first metallization portion. The second metallization portion coupled to the first metallization portion through the interconnection die such that the first integrated device and the interconnection die are located between the first metallization portion and the second metallization portion. The second metallization portion includes at least one second dielectric layer and a second plurality of metallization interconnects. The encapsulation layer coupled to the first metallization portion and the second metallization portion, wherein the encapsulation layer is located between the first metallization portion and the second metallization portion.

公开(公告)号：US20200219822A1

公开(公告)日：2020-07-09

申请号：US16241958

申请日：2019-01-07

Applicant: QUALCOMM Incorporated

Inventor： Daniel Daeik KIM ,  Manuel ALDRETE ,  Babak NEJATI

IPC: H01L23/552 ,  H01L23/00 ,  H05K1/02 ,  H01L25/065

Abstract: An RF/EMI shield has a substrate, a plurality of solder balls on a first side of the substrate, and a plurality of wire-bonds on a periphery of the first side of the substrate to form a shield which can be soldered in a surface mount process directly around components needing shielding. Each of the plurality of wire-bonds has a width selected as a fraction of the wavelength of interest.

公开(公告)号：US20180228016A1

公开(公告)日：2018-08-09

申请号：US15429144

申请日：2017-02-09

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  Jie FU ,  Manuel ALDRETE ,  Babak NEJATI ,  Husnu Ahmet MASARACIOGLU

IPC: H05K1/02 ,  H05K3/30 ,  H05K1/11 ,  H05K13/00 ,  H05K3/40

CPC classification number: H05K1/023 ,  H01L23/552 ,  H01L24/49 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/19107 ,  H01L2924/3025 ,  H05K1/0216 ,  H05K1/115 ,  H05K3/30 ,  H05K3/4038 ,  H05K9/0024 ,  H05K13/00 ,  H05K2201/0715 ,  H01L2224/45099

Abstract: In a package such as a radio frequency (RF) module, an external shield may be provided to shield the package from external influences as well as to shield the devices within the package from undesirable affecting devices outside of the package. The package may also include an internal shield to suppress adverse effects of the signal generated by an aggressor device within the external shield to other devices within the external shield.

公开(公告)号：US20170084523A1

公开(公告)日：2017-03-23

申请号：US14861619

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Jie FU ,  Daeik Daniel KIM ,  Manuel ALDRETE ,  Chin-Kwan KIM ,  David BERDY ,  Niranjan Sunil MUDAKATTE ,  Changhan YUN ,  Je-Hsiung LAN ,  Jonghae KIM

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L23/49805 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/3025 ,  H01R12/79 ,  H01L2224/81

Abstract: Conventional ways of coupling die packages to external devices include providing contacts on a separate area on a printed circuit board (PCB). These PCB contacts are configured to mate with connector contacts of a connector to enable coupling with external devices. Unfortunately, the PCB contacts take up significant amount of area of the PCB. Also, the connection can suffer from parasitic losses and signal integrity can be compromised. An on-package connection is proposed to address the short comings of the conventional ways. The on-package connection enables a die package to connect directly with the connector. This removes the need to provide a separate area for PCB contacts. Also, parasitic losses are minimized and signal integrity is enhanced.

公开(公告)号：US20160247754A1

公开(公告)日：2016-08-25

申请号：US14859318

申请日：2015-09-20

Applicant: QUALCOMM Incorporated

Inventor： Jie FU ,  Chin-Kwan KIM ,  Manuel ALDRETE ,  Milind Pravin SHAH ,  Dwayne Richard SHIRLEY

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49894 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/1533

Abstract: An integrated circuit package includes a substrate/interposer assembly having a plurality of conductive contacts and a plurality of conductive posts, such as copper posts, electrically coupled to at least some of the conductive contacts in the substrate/interposer assembly. The conductive posts are surrounded by a protective dielectric, such as a photoimageable dielectric (PID). An integrated circuit die may be disposed on the substrate/interposer assembly within an interior space surrounded by the dielectric. An additional integrated circuit die may be provided in a package-on-package (POP) configuration.

Abstract translation: 集成电路封装包括具有多个导电触点和多个导电柱（例如铜柱）的基板/插入件组件，其电耦合到衬底/插入器组件中的至少一些导电触点。 导电柱被诸如可光成像电介质（PID）的保护电介质包围。 集成电路管芯可以设置在由电介质包围的内部空间内的衬底/插入件组件上。 可以在封装封装（POP）配置中提供附加的集成电路管芯。