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公开(公告)号:US20210280507A1
公开(公告)日:2021-09-09
申请号:US16810589
申请日:2020-03-05
Applicant: QUALCOMM Incorporated
Inventor: Manuel ALDRETE , Milind SHAH , Srikanth KULKARNI
IPC: H01L23/498 , H01L23/31 , H01L23/64 , H01L21/56 , H01L21/48
Abstract: A package comprising a substrate comprising a first surface and a second surface, a passive device coupled to the first surface of the substrate, a first encapsulation layer located over the first surface of the substrate, wherein the first encapsulation layer encapsulates the passive device, an integrated device coupled to the second surface of the substrate, a second encapsulation layer located over the second surface of the substrate, wherein the second encapsulation layer encapsulates the integrated device, a plurality of through encapsulation layer interconnects coupled to the substrate, a plurality of encapsulation layer interconnects coupled to the plurality of through encapsulation layer interconnects, and at least one dummy interconnect located in the second encapsulation layer, wherein the at least one dummy interconnect is located vertically over a back side of the integrated device.
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公开(公告)号:US20190341352A1
公开(公告)日:2019-11-07
申请号:US15968774
申请日:2018-05-02
Applicant: QUALCOMM Incorporated
Inventor: Hong Bok WE , Chin-Kwan KIM , Jaehyun YEON , Manuel ALDRETE , David Fraser RAE
IPC: H01L23/552 , H01L23/31 , H01L23/498 , H01L21/48 , H01L21/56 , H01L21/78 , H01L21/683 , H01L21/3105 , H01L23/29
Abstract: A semiconductor package comprises a substrate, a die mounted on the substrate, and a mold formed over the die and on the substrate, the mold having a top surface and a plurality of tapered side surfaces, wherein the tapered side surfaces provide uniform thickness of an electromagnetic interference (EMI) shielding film.
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公开(公告)号:US20190067141A1
公开(公告)日:2019-02-28
申请号:US15691696
申请日:2017-08-30
Applicant: QUALCOMM Incorporated
Inventor: Jie FU , Hong Bok WE , Manuel ALDRETE
IPC: H01L23/31 , H01L23/00 , H01L21/78 , H01L21/56 , H01L21/027 , H01L21/683
Abstract: Conventional packages for 5G applications suffer from disadvantages including high mold stress on the die, reduced performance, and increased keep-out zone. To address these and other issues of the conventional packages, it is proposed to pre-apply a wafer-applied material, which remains in place, to form an air cavity between the die and the substrate. The air cavity can enhance the die's performance. Also, since the wafer-applied material can remain in place, the keep-out zone can be reduced. As a result, higher density modules can be fabricated.
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公开(公告)号:US20250125244A1
公开(公告)日:2025-04-17
申请号:US18605481
申请日:2024-03-14
Applicant: QUALCOMM Incorporated
Inventor: Manuel ALDRETE , Rajneesh KUMAR , Zhijie WANG , Aniket PATIL , Srikanth KULKARNI
Abstract: In an aspect, an integrated circuit (IC) package includes a base structure, an IC component disposed on the base structure, a plurality of interposer connection structures disposed on the base structure, and an interposer structure disposed over the IC component and the plurality of interposer connection structures. The plurality of interposer connection structures is configured to connect the base structure and the interposer structure. Each interposer connection structure of the plurality of interposer connection structures includes a bond ball portion that is connected to the interposer structure, and a bond wire portion that is coupled to the bond ball portion and extends toward the base structure. A width of the bond ball portion is greater than a width of the bond wire portion.
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公开(公告)号:US20250079277A1
公开(公告)日:2025-03-06
申请号:US18457162
申请日:2023-08-28
Applicant: QUALCOMM Incorporated
Inventor: Aniket PATIL , Manuel ALDRETE , Zhijie WANG , Piyush GUPTA , Rajneesh KUMAR
IPC: H01L23/498 , H01L21/48 , H01L23/31 , H01L25/10 , H10B80/00
Abstract: An integrated circuit (IC) device includes a substrate. The substrate includes a first side having a stepped configuration having a first surface that is elevated relative to a second surface. The first surface includes first solder resist openings (SROs), and the second surface includes second SROs. The IC device includes a first set of solder balls electrically connected to a first set of contacts in the first SROs. A solder ball of the first set of solder balls has a first characteristic dimension. The IC device also includes a second set of solder balls electrically connected to a second set of contacts in the second SROs. A solder ball of the second set of solder balls has a second characteristic dimension larger than the first characteristic dimension.
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公开(公告)号:US20190006999A1
公开(公告)日:2019-01-03
申请号:US15636626
申请日:2017-06-28
Applicant: QUALCOMM Incorporated
Inventor: Daeik Daniel KIM , Manuel ALDRETE , Bonhoon KOO
IPC: H03F1/30
CPC classification number: H03F1/30 , H01L23/66 , H01L2223/6677 , H03F2200/186 , H04B2001/0408
Abstract: An exemplary improved ground for a power amplifier circuit may include structural separation of the drive amplifier and the power amplifier grounds and cut-off of the power amplifier induced feedback current to ensure stability under a wide-range of operating conditions. The exemplary power amplifier may include a first ground coupled to a first amplifier circuit, a second ground coupled to a second amplifier circuit separate from the first ground, and the first amplifier circuit generates a drive current for the second amplifier circuit.
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公开(公告)号:US20180316319A1
公开(公告)日:2018-11-01
申请号:US15584000
申请日:2017-05-01
Applicant: QUALCOMM Incorporated
Inventor: Daeik Daniel KIM , Shu ZHANG , Bonhoon KOO , Manuel ALDRETE , Jie FU , Chin-Kwan KIM , Babak NEJATI , Husnu Ahmet MASARACIOGLU
IPC: H03F1/52 , H03F3/189 , H03F3/20 , H03F1/56 , H01L23/498 , H01L23/552 , H01L23/66 , H01L23/00 , H01L23/12
CPC classification number: H01L23/12 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/552 , H01L23/645 , H01L23/66 , H01L2223/6616 , H01L2223/6644 , H01L2223/6677 , H01L2224/16237 , H01L2224/48106 , H01L2224/48228 , H01L2224/48235 , H01L2224/49175
Abstract: In exemplary aspects of the disclosure, magnetic coupling problems in a power amplifier/antenna circuit may be address by using a self-shielded RF inductor mounted over the PA output match inductor embedded in the substrate to offer full RF isolation of both PA output match inductors (self-shielded and embedded) or using a self-shielded RF inductor mounted over the PA output match inductor embedded in the substrate along with a component level conformal shield around the self-shielded inductor on the assembly structure.
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公开(公告)号:US20250096051A1
公开(公告)日:2025-03-20
申请号:US18471069
申请日:2023-09-20
Applicant: QUALCOMM Incorporated
Inventor: Jaehyun YEON , Kun FANG , Suhyung HWANG , Sang-Jae LEE , Rajneesh KUMAR , Manuel ALDRETE , Zhijie WANG , Seongho KIM
IPC: H01L23/13 , H01L23/00 , H01L23/31 , H01L23/373 , H01L23/498 , H01L25/16
Abstract: A package comprising a first substrate; a first integrated device coupled to the first substrate through at least a first plurality of solder interconnects; a second substrate coupled to the first substrate through at least a second plurality of solder interconnects, wherein the second substrate includes a cavity; and an encapsulation layer located at least between the first substrate and the second substrate, wherein the encapsulation layer is coupled to the first substrate, the second substrate and the first integrated device.
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公开(公告)号:US20250070086A1
公开(公告)日:2025-02-27
申请号:US18455928
申请日:2023-08-25
Applicant: QUALCOMM Incorporated
Inventor: Aniket PATIL , Joan Rey Villarba BUOT , Michelle Yejin KIM , Manuel ALDRETE
IPC: H01L25/065 , H01L23/00 , H01L23/31 , H01L23/538
Abstract: A device includes a bottom substrate including first conductors, a top substrate including second conductors, and a first die disposed between the bottom substrate and the top substrate. The first die includes circuitry and first contacts electrically connected to the circuitry and to the first conductors. The device also includes a redistribution die disposed between the bottom substrate and the top substrate adjacent to the first die. The redistribution die includes second contacts electrically connected to the first contacts through the first conductors and third contacts electrically connected to the second conductors. The redistribution die also includes redistribution traces electrically connected to the second contacts and to the third contacts. The top substrate includes fourth contacts electrically connected through the second conductors to the third contacts to define one or more signal paths between the fourth contacts and the first die.
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公开(公告)号:US20220157705A1
公开(公告)日:2022-05-19
申请号:US17097327
申请日:2020-11-13
Applicant: QUALCOMM Incorporated
Inventor: Wen YIN , Yonghao AN , Manuel ALDRETE
IPC: H01L23/498 , H01L21/48
Abstract: Disclosed is a package and method of forming the package with a mixed pad size. The package includes a first set of pads having a first size and a first pitch, where the first set of pads are solder mask defined (SMD) pads. The package also includes a second set of pads having a second size and a second pitch, where the second set of pads are non-solder mask defined (NSMD) pads.
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