公开(公告)号：US20160218064A1

公开(公告)日：2016-07-28

申请号：US14603166

申请日：2015-01-22

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan KIM ,  David Fraser RAE ,  Rajneesh KUMAR ,  Milind Pravin SHAH ,  Omar James BCHIR

IPC: H01L23/538 ,  H01L25/16 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L23/13 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/29006 ,  H01L2224/29007 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83855 ,  H01L2224/92 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/19105 ,  H01L2224/81 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2924/00014

Abstract: A semiconductor package may include a lower substrate with one or more electronic components attached to a surface thereof and an upper substrate with one or more cavities wherein the upper substrate is attached to the lower substrate at a plurality of connection points with the one or more electronic components fitting within a single cavity or a separate cavity for each component that allow the overall form factor of the semiconductor package to remain smaller. The plurality of connection points provide a mechanical and electrical connection between the upper and lower substrate and may include solder joints there between as well as conductive filler particles that create an adhesive reinforcement matrix when compressed for assembly.

Abstract translation: 半导体封装可以包括具有附接到其表面的一个或多个电子部件的下基板和具有一个或多个空腔的上基板，其中上基板在与一个或多个电子元件的多个连接点处附接到下基板 装配在单个空腔内的部件或用于允许半导体封装的整体形状保持较小的每个部件的单独的腔体。 多个连接点在上基板和下基板之间提供机械和电连接，并且可以包括在其之间的焊接接头以及当被压缩以组装时产生粘合剂增强矩阵的导电填料颗粒。

公开(公告)号：US20150206812A1

公开(公告)日：2015-07-23

申请号：US14263823

申请日：2014-04-28

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan KIM ,  Milind Pravin SHAH ,  Manuel ALDRETE

IPC: H01L23/053 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/3205

CPC classification number: H01L23/053 ,  H01L21/30604 ,  H01L21/32051 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Methods and apparatus for cavity formation in a semiconductor package substrate are provided. In one embodiment, a method for producing at least one cavity within a semiconductor package substrate includes etching the semiconductor package substrate from a surface of the semiconductor package substrate at least one intended cavity location in order to obtain at least one cavity. The method includes depositing a copper portion on a substrate in a cavity location. Next, the method includes masking the substrate while keeping the copper portion exposed. Lastly, the method includes etching the substrate to form a cavity by etching away the copper portion. The structure formed includes a cavity that extends partially through the substrate without damaging a glass fabric embedded in the substrate.

Abstract translation: 提供了半导体封装基板中的空腔形成方法和装置。 在一个实施例中，一种用于在半导体封装衬底内产生至少一个空腔的方法包括从半导体封装衬底的表面至少一个预定的腔位置蚀刻半导体封装衬底，以便获得至少一个空腔。 该方法包括在空腔位置的基板上沉积铜部分。 接下来，该方法包括在保持铜部分暴露的同时掩蔽基板。 最后，该方法包括通过蚀刻掉铜部分来蚀刻基板以形成空腔。 所形成的结构包括部分地延伸穿过基底的空腔，而不会损害嵌入在基底中的玻璃织物。

公开(公告)号：US20160247754A1

公开(公告)日：2016-08-25

申请号：US14859318

申请日：2015-09-20

Applicant: QUALCOMM Incorporated

Inventor： Jie FU ,  Chin-Kwan KIM ,  Manuel ALDRETE ,  Milind Pravin SHAH ,  Dwayne Richard SHIRLEY

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49894 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/1533

Abstract: An integrated circuit package includes a substrate/interposer assembly having a plurality of conductive contacts and a plurality of conductive posts, such as copper posts, electrically coupled to at least some of the conductive contacts in the substrate/interposer assembly. The conductive posts are surrounded by a protective dielectric, such as a photoimageable dielectric (PID). An integrated circuit die may be disposed on the substrate/interposer assembly within an interior space surrounded by the dielectric. An additional integrated circuit die may be provided in a package-on-package (POP) configuration.

Abstract translation: 集成电路封装包括具有多个导电触点和多个导电柱（例如铜柱）的基板/插入件组件，其电耦合到衬底/插入器组件中的至少一些导电触点。 导电柱被诸如可光成像电介质（PID）的保护电介质包围。 集成电路管芯可以设置在由电介质包围的内部空间内的衬底/插入件组件上。 可以在封装封装（POP）配置中提供附加的集成电路管芯。