公开(公告)号：US20160142054A1

公开(公告)日：2016-05-19

申请号：US14639755

申请日：2015-03-05

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Kern Rim ,  Choh Fei Yeap

IPC: H03K19/00 ,  H03K19/0185

CPC classification number: H03K19/0016 ,  G06F1/3206 ,  G06F1/3212 ,  G06F1/3296 ,  G06F17/505 ,  G06F2209/5019 ,  G06F2217/68 ,  G06F2217/78 ,  H03K19/018507 ,  Y02D10/172 ,  Y02D10/174

Abstract: A method for scaling voltages provided to different modules of a system-on-chip (SOC) includes receiving, at an energy-performance engine of the SOC, a first indication of usage history for a first module of the SOC and a second indication of usage history for a second module of the SOC. The method includes receiving a battery life indication that indicates a remaining battery life for a battery of the SOC. The method also includes adjusting a first supply voltage provided to the first module of the SOC based on the first indication, the second indication, and the battery life indication. The method further includes adjusting a second supply voltage provided to the second module of the SOC based on the first indication, the second indication, and the battery life indication.

Abstract translation: 一种用于缩放提供给片上系统（SOC）的不同模块的电压的方法包括在SOC的能量性能引擎处接收SOC的第一模块的使用历史的第一指示，以及SOC的第一指示 SOC的第二个模块的使用历史。 该方法包括接收指示SOC的电池的剩余电池寿命的电池寿命指示。 该方法还包括基于第一指示，第二指示和电池寿命指示来调整提供给SOC的第一模块的第一电源电压。 该方法还包括基于第一指示，第二指示和电池寿命指示来调整提供给SOC的第二模块的第二电源电压。

公开(公告)号：US09165929B2

公开(公告)日：2015-10-20

申请号：US14322207

申请日：2014-07-02

Applicant: QUALCOMM Incorporated

Inventor： Kern Rim ,  Jeffrey Junhao Xu ,  Stanley Seungchul Song

IPC: H01L27/12 ,  H01L27/092 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161

Abstract: A complementary fin field-effect transistor (FinFET) includes a p-type device having a p-channel fin. The p-channel fin may include a first material that is lattice mismatched relative to a semiconductor substrate. The first material may have a compressive strain. The FinFET device also includes an n-type device having an re-channel fin. The n-channel fin may include a second material having a tensile strain that is lattice mismatched relative to the semiconductor substrate. The p-type device and the n-type device cooperate to form the complementary FinFET device.

Abstract translation: 互补翅片场效应晶体管（FinFET）包括具有p沟道鳍片的p型器件。 p沟道鳍可以包括相对于半导体衬底而晶格失配的第一材料。 第一种材料可能具有压缩应变。 FinFET器件还包括具有再通道鳍片的n型器件。 n沟道翅片可以包括具有相对于半导体衬底的晶格失配的拉伸应变的第二材料。 p型器件和n型器件配合形成互补FinFET器件。

公开(公告)号：US20150270134A1

公开(公告)日：2015-09-24

申请号：US14284958

申请日：2014-05-22

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Kern Rim ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC: H01L21/285 ,  H01L29/66 ,  C23C14/54 ,  C23C16/52 ,  C23C16/46 ,  C23C14/24 ,  H01L21/324 ,  H01L29/45

CPC classification number: H01L21/823814 ,  C23C14/24 ,  C23C14/54 ,  C23C16/46 ,  C23C16/52 ,  H01L21/285 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/324 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/66568

Abstract: A method includes forming a first metal layer on source/drain regions of an n-type metal-oxide-semiconductor (NMOS) device and on source/drain regions of a p-type MOS (PMOS) device by chemical vapor deposition (CVD) or non-energetic physical vapor deposition (PVD). The method further includes selectively performing a rapid thermal anneal (RTA) process on the first metal layer after forming the first metal layer.

Abstract translation: 一种方法包括通过化学气相沉积（CVD）在n型金属氧化物半导体（NMOS）器件的源极/漏极区域和p型MOS（PMOS）器件的源极/漏极区域上形成第一金属层， 或非能量物理气相沉积（PVD）。 该方法还包括在形成第一金属层之后在第一金属层上选择性地执行快速热退火（RTA）工艺。

公开(公告)号：US20150262875A1

公开(公告)日：2015-09-17

申请号：US14471086

申请日：2014-08-28

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Kern Rim ,  Choh Fei Yeap

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L21/76879 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76885

Abstract: A method includes forming an electronic device structure including a substrate, an oxide layer, and a first low-k layer. The method also includes forming openings by patterning the oxide layer, filling the openings with a conductive material to form conductive structures within the openings, and removing the oxide layer using the first low-k layer as an etch stop layer. The conductive structures contact the first low-k layer. Removing the oxide layer includes performing a chemical vapor etch process with respect to the oxide layer to form an etch byproduct and removing the etch byproduct. The method includes forming a second low-k layer using a deposition process that causes the second low-k layer to define one or more cavities. Each cavity is defined between a first conductive structure and an adjacent conductive structure, the first and second conductive structures have a spacing therebetween that is smaller than a threshold distance.

Abstract translation: 一种方法包括形成包括衬底，氧化物层和第一低k层的电子器件结构。 该方法还包括通过图案化氧化物层来形成开口，用导电材料填充开口以在开口内形成导电结构，以及使用第一低k层作为蚀刻停止层去除氧化物层。 导电结构接触第一低k层。 去除氧化物层包括相对于氧化物层执行化学气相蚀刻工艺以形成蚀刻副产物并除去蚀刻副产物。 该方法包括使用使第二低k层限定一个或多个空腔的沉积工艺形成第二低k层。 每个空腔限定在第一导电结构和相邻的导电结构之间，第一和第二导电结构之间具有小于阈值距离的间隔。

公开(公告)号：US11545555B2

公开(公告)日：2023-01-03

申请号：US16944624

申请日：2020-07-31

Applicant: QUALCOMM Incorporated

Inventor： Peijie Feng ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L29/423 ,  H01L29/167 ,  H01L29/78 ,  H01L29/06

Abstract: Gate-all-around (GAA) transistors with shallow source/drain regions and methods of fabricating the same provide a GAA transistor that includes one or more channels positioned between a source region and a drain region. The one or more channels, which may be nanowire, nanosheet, or nanoslab semiconductors, are surrounded along a longitudinal axis by gate material. At a first end of the channel is a source region and at an opposite end of the channel is a drain region. To reduce parasitic capacitance between a bottom gate and the source and drain regions, a filler material is provided adjacent the bottom gate, and the source and drain regions are grown on top of the filler material. In this fashion, the bottom gate does not abut the source region or the drain region, reducing geometries which would contribute to parasitic capacitance.

公开(公告)号：US11302638B2

公开(公告)日：2022-04-12

申请号：US16738127

申请日：2020-01-09

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/535

Abstract: Certain aspects of the present disclosure generally relate to integration of a hybrid conductor material in power rails of a semiconductor device. An example semiconductor device generally includes an active electrical device and a power rail. The power rail is electrically coupled to the active electrical device, disposed above the active electrical device, and embedded in at least one dielectric layer. The power rail includes a first conductive layer, a barrier layer, and a second conductive layer. In certain cases, copper may be used as conductive material for the second conductive layer. The barrier layer is disposed between the first conductive layer and the second conductive layer.

公开(公告)号：US10700204B2

公开(公告)日：2020-06-30

申请号：US16104522

申请日：2018-08-17

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Kern Rim ,  Da Yang ,  Peijie Feng

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/165

Abstract: Cell circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation and related methods are disclosed. In one aspect, a cell circuit includes a substrate of semiconductor material and a semiconductor channel structure(s) of a second semiconductor material disposed on the substrate. The semiconductor material applies a stress to the formed semiconductor channel structure(s) to induce a strain in the semiconductor channel structure(s) for increasing carrier mobility. A diffusion break comprising a dielectric material extends through a surrounding structure of an interlayer dielectric, and the semiconductor channel structure(s) and at least a portion of the substrate. The relaxation of strain in areas of the semiconductor channel structure(s) adjacent to the diffusion break is reduced or avoided, because the semiconductor channel structure(s) is constrained by the surrounding structure.

公开(公告)号：US20200006122A1

公开(公告)日：2020-01-02

申请号：US16020096

申请日：2018-06-27

Applicant: QUALCOMM Incorporated

Inventor： Mustafa Badaroglu ,  Kern Rim

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/528 ,  H01L21/311

Abstract: Integrated circuits (ICs) made using extreme ultraviolet (EUV) patterning and methods for fabricating such ICs are disclosed. In an exemplary aspect, fabricating such ICs includes using a double-exposure EUV process when making metal trenches for the ICs. In particular, after a first EUV exposure and etching process, spacers are used before a second EUV exposure to guarantee minimum spacing between the metal trenches.

公开(公告)号：US10411091B1

公开(公告)日：2019-09-10

申请号：US16034746

申请日：2018-07-13

Applicant: QUALCOMM Incorporated

Inventor： Mustafa Badaroglu ,  Kern Rim

IPC: H01L29/06 ,  H01L29/66 ,  H01L27/092 ,  H01L29/417 ,  H01L29/40 ,  H01L29/78

Abstract: Integrated circuits employing a field gate(s) without dielectric layers and/or work function metal layers for reduced gate layout parasitic resistance, and related methods are disclosed. At least a portion of the dielectric layers and/or work function metal layers present in active gate(s) is not present in a field gate(s) of a gate in a circuit cell. The field gate(s) have more conductive gate material than the active gate(s). In this manner, the increased volume of gate material in the field gate(s) reduces gate layout parasitic resistance. The active gate(s) retains the dielectric layers and/or work function metal layers to effectively isolate the gate material from a channel of a FET formed from the circuit cell to provide effective channel control. Reducing gate layout parasitic resistance can reduce current (I) resistance (R) (IR) drop to achieve the desired drive strength in the integrated circuit.

公开(公告)号：US09997360B2

公开(公告)日：2018-06-12

申请号：US15271867

申请日：2016-09-21

Applicant: QUALCOMM Incorporated

Inventor： Da Yang ,  Yanxiang Liu ,  Jun Yuan ,  Kern Rim

IPC: H01L29/76 ,  H01L21/28 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3213

CPC classification number: H01L21/28123 ,  H01L21/32139 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.