公开(公告)号：US09871121B2

公开(公告)日：2018-01-16

申请号：US14341568

申请日：2014-07-25

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Kern Rim ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  Vladimir Machkaoutsan ,  Da Yang ,  Choh Fei Yeap

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/6681 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: In a particular embodiment, a method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.

公开(公告)号：US09859210B2

公开(公告)日：2018-01-02

申请号：US14744912

申请日：2015-06-19

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Choh Fei Yeap ,  Da Yang

IPC: H01L23/528 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/02 ,  H01L27/092 ,  H01L27/12 ,  H01L23/522 ,  H01L27/088 ,  H01L29/78 ,  H01L23/48 ,  H01L23/525

CPC classification number: H01L23/528 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/845 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1211

Abstract: In a particular aspect, an integrated circuit includes a first transistor including a first source region and a first drain region. The integrated circuit includes a second transistor including a second source region and a second drain region. The integrated circuit includes a first gate structure coupled to the first transistor and to the second transistor. The first gate structure is included in a first layer. The integrated circuit further includes a first metal line coupled to the first source region and to the second drain region. The first metal line has a two-dimensional routing arrangement and is included in a second layer that is distinct from the first layer.

公开(公告)号：US20170338215A1

公开(公告)日：2017-11-23

申请号：US15160992

申请日：2016-05-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Giridhar Nallapati ,  Da Yang ,  Kern Rim ,  Robert Bucki ,  Choh Fei Yeap

IPC: H01L27/02 ,  H01L27/092 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/11803 ,  H01L28/00 ,  H01L2027/11809 ,  H01L2027/11824 ,  H01L2027/11874 ,  H01L2027/11881

Abstract: A heterogeneous cell array includes a first column of cells and a second column of cells. The first column of cells includes a first cell having a first area and a second cell having the first area. The first cell includes two fin-type field effect transistors having a first number of fins and the second cell includes two fin-type field effect transistors having the first number of fins. The second column of cells includes a third cell having a second area. The third cell is adjacent to the first cell and to the second cell, and the third cell includes two fin-type field effect transistors having a second number of fins. The second area is greater than the first area, and the second number of fins is greater than the first number of fins.

公开(公告)号：US09620454B2

公开(公告)日：2017-04-11

申请号：US14484366

申请日：2014-09-12

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Kern Rim ,  Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Da Yang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L23/528 ,  H01L27/02 ,  H01L23/522

CPC classification number: H01L23/53257 ,  H01L21/0217 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via are disclosed. Related methods are also disclosed. In particular, different metal lines in a metal layer may need to be electrically interconnected during a MOL process for an IC. In this regard, to allow for metal lines to be interconnected without providing such interconnections above the metal lines that may be difficult to provide in a printing process for example, in an exemplary aspect, an elongated or expanded via(s) is provided in a MOL layer in an IC. The elongated via is provided in the MOL layer below the metal layer in the MOL layer and extended across two or more adjacent metal layers in the metal layer of the MOL layer. Moving the interconnections above the MOL layer can simplify the manufacturing of ICs, particularly at low nanometer (nm) node sizes.

公开(公告)号：US20160372414A1

公开(公告)日：2016-12-22

申请号：US14744912

申请日：2015-06-19

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Choh Fei Yeap ,  Da Yang

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L23/528 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/845 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1211

Abstract: In a particular aspect, an integrated circuit includes a first transistor including a first source region and a first drain region. The integrated circuit includes a second transistor including a second source region and a second drain region. The integrated circuit includes a first gate structure coupled to the first transistor and to the second transistor. The first gate structure is included in a first layer. The integrated circuit further includes a first metal line coupled to the first source region and to the second drain region. The first metal line has a two-dimensional routing arrangement and is included in a second layer that is distinct from the first layer.

Abstract translation: 在特定方面，集成电路包括包括第一源极区域和第一漏极区域的第一晶体管。 集成电路包括包括第二源区和第二漏区的第二晶体管。 集成电路包括耦合到第一晶体管和第二晶体管的第一栅极结构。 第一栅极结构被包括在第一层中。 集成电路还包括耦合到第一源极区域和第二漏极区域的第一金属线路。 第一金属线具有二维布线布置，并且包括在与第一层不同的第二层中。

公开(公告)号：US11152347B2

公开(公告)日：2021-10-19

申请号：US15952638

申请日：2018-04-13

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Kern Rim ,  John Jianhong Zhu ,  Da Yang

IPC: H01L27/02 ,  H01L23/48 ,  H03K3/3562 ,  H01L27/118

Abstract: Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections. In exemplary aspects disclosed herein, to allow cross-connections to be made across different gates between PMOS and NMOS transistors formed in the circuit cell, cut areas in the circuit cell are located in different horizontal routing tracks and offset from each other in the direction of longitudinal axes of gates. Gate cross-connections can be routed around offset gate cut areas and coupled to active gates to form gate cross-connections. In this manner, fewer metal layers may be required to provide such cross-connections in the circuit cell, thus reducing area. Further, gate contacts of cross-connected gates can be formed as gate contacts over active areas (GCOAs) in diffusion areas of the circuit cell, thus facilitating easier routing of interconnections in non-diffusion area of the circuit cell for further ease of routing.

公开(公告)号：US10763364B1

公开(公告)日：2020-09-01

申请号：US16895909

申请日：2020-06-08

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Kern Rim ,  Da Yang ,  Peijie Feng

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L29/165 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/66

Abstract: Cell circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation and related methods are disclosed. In one aspect, a cell circuit includes a substrate of semiconductor material and a semiconductor channel structure(s) of a second semiconductor material disposed on the substrate. The semiconductor material applies a stress to the formed semiconductor channel structure(s) to induce a strain in the semiconductor channel structure(s) for increasing carrier mobility. A diffusion break comprising a dielectric material extends through a surrounding structure of an interlayer dielectric, and the semiconductor channel structure(s) and at least a portion of the substrate. The relaxation of strain in areas of the semiconductor channel structure(s) adjacent to the diffusion break is reduced or avoided, because the semiconductor channel structure(s) is constrained by the surrounding structure.

公开(公告)号：US10559501B2

公开(公告)日：2020-02-11

申请号：US15271043

申请日：2016-09-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley Song ,  Jeffrey Xu ,  Da Yang ,  Kern Rim ,  Choh Fei Yeap

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/66 ,  H01L21/3065

Abstract: A method of producing a FinFET device with fin pitch of less than 20 nm is presented. In accordance with some embodiments, fins are deposited on sidewall spacers, which themselves are deposited on mandrels. The mandrels can be formed by lithographic processes while the fins and sidewall spacers formed by deposition technologies.

公开(公告)号：US20190319022A1

公开(公告)日：2019-10-17

申请号：US15952638

申请日：2018-04-13

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Kern Rim ,  John Jianhong Zhu ,  Da Yang

IPC: H01L27/02 ,  H01L27/118 ,  H03K3/3562 ,  H01L23/48

Abstract: Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections. In exemplary aspects disclosed herein, to allow cross-connections to be made across different gates between PMOS and NMOS transistors formed in the circuit cell, cut areas in the circuit cell are located in different horizontal routing tracks and offset from each other in the direction of longitudinal axes of gates. Gate cross-connections can be routed around offset gate cut areas and coupled to active gates to form gate cross-connections. In this manner, fewer metal layers may be required to provide such cross-connections in the circuit cell, thus reducing area. Further, gate contacts of cross-connected gates can be formed as gate contacts over active areas (GCOAs) in diffusion areas of the circuit cell, thus facilitating easier routing of interconnections in non-diffusion area of the circuit cell for further ease of routing.

公开(公告)号：US20180033729A1

公开(公告)日：2018-02-01

申请号：US15634039

申请日：2017-06-27

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Mustafa Badaroglu ,  Da Yang ,  Periannan Chidambaram

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L27/02

CPC classification number: H01L23/5283 ,  G06F17/5072 ,  H01L21/76895 ,  H01L23/5286 ,  H01L23/53209 ,  H01L23/53252 ,  H01L23/53257 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11881

Abstract: Standard cell circuits employing high aspect ratio voltage rails for reduced resistance are disclosed. In one aspect, a standard cell circuit is provided that employs a first high aspect ratio voltage rail configured to receive a first supply voltage. A second high aspect ratio voltage rail is employed that is disposed substantially parallel to the first high aspect ratio voltage rail. A voltage differential between the first and second high aspect ratio voltage rails is used to power a circuit device in the standard cell circuit. The first and second high aspect ratio voltage rails each have a height-to-width ratio greater than 1.0. The height of each respective first and second high aspect ratio voltage rail is greater than each respective width. Employing the first and second high aspect ratio voltage rails allows each to have a cross-sectional area that limits the resistance and corresponding IR drop.