公开(公告)号：US09263186B2

公开(公告)日：2016-02-16

申请号：US13785502

申请日：2013-03-05

Applicant: QUALCOMM Incorporated

Inventor： Yue Li ,  Xiaoming Chen ,  Zhongping Bao ,  Charles D. Paynter ,  Xiaonan Zhang ,  Ryan D. Lane

IPC: H01L49/02 ,  H01G2/06 ,  H01L23/50 ,  H01L23/64 ,  H01L23/00 ,  H01G4/38 ,  H01G4/40 ,  H01L23/498

CPC classification number: H01G2/06 ,  H01G4/38 ,  H01G4/40 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L24/17 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Some implementations provide a semiconductor device that includes a first substrate, a die coupled to the first substrate, and a set of solder balls coupled to the first substrate. The set of solder balls is configured to provide an electrical connection between the die and a second substrate. The semiconductor device also includes at least one decoupling capacitor coupled to the die through the first substrate. The at least one decoupling capacitor is configured to provide an electrical connection between the die and the second substrate. The at least one decoupling capacitor is coupled to the first substrate such that the at least one decoupling capacitor is positioned between the first substrate and the second substrate. In some implementations, the second substrate is a printed circuit board (PCB). In some implementations, the first substrate is a first package substrate, and the second substrate is a second package substrate.

Abstract translation: 一些实施方式提供一种半导体器件，其包括第一衬底，耦合到第一衬底的管芯和耦合到第一衬底的一组焊球。 该组焊球被配置成在管芯和第二衬底之间提供电连接。 半导体器件还包括通过第一衬底耦合到管芯的至少一个去耦电容器。 所述至少一个去耦电容器被配置为在所述管芯和所述第二衬底之间提供电连接。 所述至少一个去耦电容器耦合到所述第一衬底，使得所述至少一个去耦电容器位于所述第一衬底和所述第二衬底之间。 在一些实施方案中，第二衬底是印刷电路板（PCB）。 在一些实施方案中，第一衬底是第一封装衬底，第二衬底是第二封装衬底。

公开(公告)号：US10170232B2

公开(公告)日：2019-01-01

申请号：US14931659

申请日：2015-11-03

Applicant: QUALCOMM Incorporated

Inventor： Yue Li ,  Charles David Paynter ,  Ryan David Lane

IPC: H01F27/28 ,  H01F27/29 ,  H01L27/08 ,  H01F41/04 ,  H05K1/18 ,  H01F17/00 ,  H01F17/02

Abstract: A toroid inductor includes a plurality of first turns configured in a first ring shape and a plurality of second turns configured in a second ring shape. The plurality of first turns includes a plurality of first upper interconnects, a plurality of first lower interconnects, and a plurality of first vias coupled to the plurality of first upper interconnects and to the plurality of first lower interconnects. The plurality of second turns is at least partially intertwined with the plurality of first turns. The plurality of second turns includes a plurality of second upper interconnects, a plurality of second lower interconnects, and a plurality of second vias coupled to the plurality of second upper interconnects and to the plurality of second lower interconnects.

公开(公告)号：US20170064837A1

公开(公告)日：2017-03-02

申请号：US14842403

申请日：2015-09-01

Applicant: QUALCOMM Incorporated

Inventor： Yue Li ,  Charles David Paynter ,  Ryan David Lane ,  Ruey Kae Zang

IPC: H05K1/18 ,  H01L21/56 ,  H01L23/498 ,  H05K1/03 ,  H05K1/11

CPC classification number: H05K1/186 ,  H01L21/4857 ,  H01L21/50 ,  H01L21/56 ,  H01L23/13 ,  H01L23/16 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/64 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19106 ,  H05K1/0306 ,  H05K1/0313 ,  H05K1/113 ,  H05K1/114 ,  H05K2201/10015 ,  H05K2201/1003 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An integrated circuit (IC) module that includes an integrated circuit (IC) package, a plurality of first solder interconnects coupled to the IC package, an interposer coupled to the IC package through the plurality of first solder interconnects a plurality of second solder interconnects coupled to the interposer; and a printed circuit board (PCB) coupled to the interposer through the plurality of second solder interconnects. The interposer includes an encapsulation layer, a first passive component at least partially embedded in the encapsulation layer, and a plurality of interconnects coupled to the first passive component. The encapsulation layer includes a mold and/or an epoxy fill. The first passive component is configured to operate as an electronic voltage regulator (EVR) for the IC module. In some implementations, the interposer is a fan out interposer.

Abstract translation: 一种集成电路（IC）模块，其包括集成电路（IC）封装，耦合到所述IC封装的多个第一焊料互连件，通过所述多个第一焊料互连而耦合到所述IC封装的插入件，多个第二焊料互连 到中介者 以及通过所述多个第二焊料互连件耦合到所述插入件的印刷电路板（PCB）。 插入器包括封装层，至少部分地嵌入封装层中的第一无源元件以及耦合到第一无源元件的多个互连。 封装层包括模具和/或环氧树脂填充物。 第一个无源组件配置为作为IC模块的电子稳压器（EVR）运行。 在一些实现中，插入器是扇出插件。

公开(公告)号：US09350339B2

公开(公告)日：2016-05-24

申请号：US14335681

申请日：2014-07-18

Applicant: QUALCOMM Incorporated

Inventor： Thomas Clark Bryan ,  Alvin Leng Sun Loke ,  Stephen Knol ,  Gregory Francis Lynch ,  Tin Tin Wee ,  LuVerne Ray Peterson ,  Yue Li

IPC: H03K3/00 ,  H03K5/15 ,  H01L23/538 ,  G06F1/10 ,  G11C7/22 ,  H01L25/065

CPC classification number: H03K5/15013 ,  G06F1/10 ,  G11C7/22 ,  H01L23/5384 ,  H01L23/5389 ,  H01L25/0655 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2924/15311

Abstract: Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.

Abstract translation: 提供了芯片到芯片时钟分配的电路。 系统包括第一管芯上的传输时钟树和第二管芯上的接收时钟树。 发送时钟树和接收时钟树是相同的或非常接近相同的，所以发送时钟树上的给定位的插入延迟与对应于给定位的位的插入延迟相同 接收时钟树。 虽然在同一个时钟树中可能存在从位到位的时钟偏差，但是不同芯片上的相应位具有相同的时钟插入延迟。

公开(公告)号：US20150313006A1

公开(公告)日：2015-10-29

申请号：US14264836

申请日：2014-04-29

Applicant: QUALCOMM Incorporated

Inventor： Ryan David Lane ,  Yue Li ,  Charles David Paynter ,  Ruey Kae Zang

IPC: H05K1/02 ,  H01L21/48 ,  H05K3/00 ,  H01L23/528 ,  H01L23/498 ,  H01L21/768 ,  H01L23/522

CPC classification number: H05K1/0216 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/5286 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0225 ,  H05K1/0236 ,  H05K2201/09309

Abstract: Some novel features pertain to an integrated device that includes a first metal layer and a second metal layer. The first metal layer includes a first set of regions. The first set of regions includes a first netlist structure for a power distribution network (PDN) of the integrated device. The second metal layer includes a second set of regions. The second set of regions includes a second netlist structure of the PDN of the integrated device. In some implementations, the second metal layer further includes a third set of regions comprising the first netlist structure for the PDN of the integrated device. In some implementations, the first metal layer includes a third set of regions that includes a third netlist structure for the PDN of the integrated device. The third set of regions is non-overlapping with the first set of regions of the first metal layer.

Abstract translation: 一些新颖的特征涉及包括第一金属层和第二金属层的集成器件。 第一金属层包括第一组区域。 第一组区域包括用于集成设备的配电网络（PDN）的第一网表结构。 第二金属层包括第二组区域。 第二组区域包括集成设备的PDN的第二网表结构。 在一些实现中，第二金属层还包括第三组区域，其包括用于集成设备的PDN的第一网表结构。 在一些实现中，第一金属层包括第三组区域，其包括用于集成设备的PDN的第三网表结构。 第三组区域与第一金属层的第一组区域不重叠。

公开(公告)号：US20140252544A1

公开(公告)日：2014-09-11

申请号：US13785502

申请日：2013-03-05

Applicant: QUALCOMM INCORPORATED

Inventor： Yue Li ,  Xiaoming Chen ,  Zhongping Bao ,  Charles D. Paynter ,  Xiaonan Zhang ,  Ryan D. Lane

IPC: H01L49/02

CPC classification number: H01G2/06 ,  H01G4/38 ,  H01G4/40 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L24/17 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Some implementations provide a semiconductor device that includes a first substrate, a die coupled to the first substrate, and a set of solder balls coupled to the first substrate. The set of solder balls is configured to provide an electrical connection between the die and a second substrate. The semiconductor device also includes at least one decoupling capacitor coupled to the die through the first substrate. The at least one decoupling capacitor is configured to provide an electrical connection between the die and the second substrate. The at least one decoupling capacitor is coupled to the first substrate such that the at least one decoupling capacitor is positioned between the first substrate and the second substrate. In some implementations, the second substrate is a printed circuit board (PCB). In some implementations, the first substrate is a first package substrate, and the second substrate is a second package substrate.

Abstract translation: 一些实施方式提供一种半导体器件，其包括第一衬底，耦合到第一衬底的管芯和耦合到第一衬底的一组焊球。 该组焊球被配置成在管芯和第二衬底之间提供电连接。 半导体器件还包括通过第一衬底耦合到管芯的至少一个去耦电容器。 所述至少一个去耦电容器被配置为在所述管芯和所述第二衬底之间提供电连接。 所述至少一个去耦电容器耦合到所述第一衬底，使得所述至少一个去耦电容器位于所述第一衬底和所述第二衬底之间。 在一些实施方案中，第二衬底是印刷电路板（PCB）。 在一些实施方案中，第一衬底是第一封装衬底，第二衬底是第二封装衬底。

公开(公告)号：US20240421119A1

公开(公告)日：2024-12-19

申请号：US18336331

申请日：2023-06-16

Applicant: QUALCOMM Incorporated

Inventor： Yangyang Sun ,  Yue Li ,  Lily Zhao ,  Piyush Gupta ,  Xuefeng Zhang

IPC: H01L23/00

Abstract: Flexible under-bump metallization sizes and patterning, and related integrated circuit packages and fabrication methods are disclosed. First under-bump metallizations (UBMs) of a first, larger size and pitch are provided in the die and coupled to corresponding metal interconnects in the package substrate. One or more second UBMs of a second, reduced size UBMs can also be located in the core area of the die. This provides greater flexibility in the design and layout of the die, because different circuits within the die (e.g., I/O related circuits) may only require coupling to smaller size UBMs for performance requirements and thus can be more flexibility located in the die. Also, to further reduce pitch of the second, smaller size UBMs, one or more of the second, smaller size UBMs can be formed as oblong-shaped UBMs, which can still maintain a minimum separation based on metal interconnect pitch limitations in the package substrate.

公开(公告)号：US11817406B2

公开(公告)日：2023-11-14

申请号：US17483325

申请日：2021-09-23

Applicant: QUALCOMM Incorporated

Inventor： Yue Li ,  Durodami Lisk ,  Jinying Sun

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2225/0652 ,  H01L2225/06517

Abstract: A semiconductor die (“die”) employing repurposed seed layer for forming additional signal paths to a back end-of-line (BEOL) structure of the die, and related integrated circuit (IC) packages and fabrication methods. A seed layer is repurposed that was disposed adjacent the BEOL interconnect structure to couple an under bump metallization (UBM) interconnect without a coupled interconnect bump thus forming an unraised interconnect bump, to a UBM interconnect that has a raised interconnect bump. To couple the unraised interconnect bump to the raised interconnect bump, the seed layer is selectively removed during fabrication to leave a portion of the seed layer repurposed that couples the UBM interconnect that does not have an interconnect bump to the UBM interconnect that has a raised interconnect bump. Additional routing paths can be provided between raised interconnect bumps to the BEOL interconnect structure through coupling of UBM interconnects to an unraised interconnect bump.

公开(公告)号：US20230102167A1

公开(公告)日：2023-03-30

申请号：US17484475

申请日：2021-09-24

Applicant: QUALCOMM Incorporated

Inventor： Darko Popovic ,  Durodami Lisk ,  Yue Li

IPC: H01L25/10 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

Abstract: Multiple (multi-) die integrated circuit (IC) packages for supporting higher connection density, and related fabrication methods. The multi-die IC package includes split dies that provided in respective die packages that are stacked on top of each other to conserve package area. To support signal routing, including through-package signal routing that extends through the die package, each die package includes vertical interconnects disposed adjacent to their respective dies and coupled to a respective package substrate (and interposer substrate if provided) in the package substrate. In this manner, as an example, through-silicon-vias (TSVs) are not required to be fabricated in the multi-die IC package that extend through the dies themselves to provide signal routing between the respective die packages. In another example, space created between adjacent interposer substrates of stacked die packages, as stood off from each other through the interconnect bumps, provides an area for heat dissipation.

公开(公告)号：US11380613B2

公开(公告)日：2022-07-05

申请号：US16888516

申请日：2020-05-29

Applicant: QUALCOMM Incorporated

Inventor： Yue Li ,  Li-Sheng Weng ,  Yangyang Sun

IPC: H01L23/50 ,  H01L23/00

Abstract: An integrated circuit (IC) package is described. The IC package includes a die, having a pad layer structure on back-end-of-line layers on a substrate. The die also includes a metallization routing layer on the pad layer structure, and a first under bump metallization layer on the metallization routing layer. The IC package also includes a patterned seed layer on a surface of the die to contact the first under bump metallization layer. The IC package further includes a first package bump on the first under bump metallization layer.