公开(公告)号：US09691694B2

公开(公告)日：2017-06-27

申请号：US14703290

申请日：2015-05-04

Applicant: QUALCOMM Incorporated

Inventor： Uei-Ming Jow ,  Young Kyu Song ,  Jong-Hoon Lee ,  Xiaonan Zhang ,  Mario Francisco Velez

IPC: H01L23/48 ,  H01L21/336 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/50

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/15311

Abstract: An integrated circuit device that includes a package substrate and a die coupled to the package substrate. The package substrate includes at least one dielectric layer, a first stack of first interconnects in the at least one dielectric layer, and a second interconnect formed on at least one side portion of the at least one dielectric layer. The first stack of first interconnects is configured to provide a first electrical path for a non-ground reference signal, where the first stack of first interconnects is located along at least one side of the package substrate. The second interconnect is configured to provide a second electrical path for a ground reference signal.

公开(公告)号：US09373583B2

公开(公告)日：2016-06-21

申请号：US14323907

申请日：2014-07-03

Applicant: QUALCOMM Incorporated

Inventor： Jong-Hoon Lee ,  Young Kyu Song ,  Jung Ho Yoon ,  Uei Ming Jow ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H01L27/08 ,  H01L23/522 ,  H01L49/02 ,  H01L23/64 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11 ,  H01L23/00 ,  H01L25/03 ,  H01L23/525

CPC classification number: H01L23/5227 ,  H01L23/5223 ,  H01L23/525 ,  H01L23/645 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/117 ,  H01L28/10 ,  H01L28/40 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81447 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15331 ,  H01L2924/15788 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Some implementations provide an integrated device that includes a capacitor and an inductor. The inductor is electrically coupled to the capacitor. The inductor and the capacitor are configured to operate as a filter for an electrical signal in the integrated device. The inductor includes a first metal layer of a printed circuit board (PCB), a set of solder balls coupled to the PCB, and a second metal layer in a die. In some implementations, the capacitor is located in the die. In some implementations, the capacitor is a surface mounted passive device on the PCB. In some implementations, the first metal layer is a trace on the PCB. In some implementations, the inductor includes a third metal layer in the die. In some implementations, the second metal layer is an under bump metallization (UBM) layer of the die, and the third metal is a redistribution layer of the die.

Abstract translation: 一些实施方案提供了包括电容器和电感器的集成器件。 电感器电耦合到电容器。 电感器和电容器被配置为在集成器件中用作电信号的滤波器。 电感器包括印刷电路板（PCB）的第一金属层，耦合到PCB的一组焊球，以及模具中的第二金属层。 在一些实施方案中，电容器位于管芯中。 在一些实现中，电容器是PCB上的表面安装无源器件。 在一些实施方案中，第一金属层是PCB上的痕迹。 在一些实施方案中，电感器包括管芯中的第三金属层。 在一些实施方案中，第二金属层是管芯的凸块下金属化（UBM）层，第三金属是管芯的再分布层。

公开(公告)号：US09368566B2

公开(公告)日：2016-06-14

申请号：US14334521

申请日：2014-07-17

Applicant: QUALCOMM Incorporated

Inventor： Jong-Hoon Lee ,  Young Kyu Song ,  Daeik Daniel Kim ,  Jung Ho Yoon ,  Uei-Ming Jow ,  Mario Francisco Velez ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H01L29/00 ,  H01L49/02 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L28/40 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311

Abstract: Some features pertain to an integrated device (e.g., package-on-package (PoP) device) that includes a substrate, a first die, a first encapsulation layer, a first redistribution portion, a second die, a second encapsulation layer, and a second redistribution portion. The substrate includes a first surface and a second surface. The substrate includes a capacitor. The first die is coupled to the first surface of the substrate. The first encapsulation layer encapsulates the first die. The first redistribution portion is coupled to the first encapsulation. The second die is coupled to the second surface of the substrate. The second encapsulation layer encapsulates the second die. The second redistribution portion is coupled to the second encapsulation layer.

Abstract translation: 一些特征涉及包括衬底，第一管芯，第一封装层，第一再分配部分，第二管芯，第二封装层和第二封装层的集成器件（例如，封装封装（PoP）器件） 第二再分配部分。 基板包括第一表面和第二表面。 基板包括电容器。 第一管芯耦合到衬底的第一表面。 第一封装层封装第一裸片。 第一再分配部分耦合到第一封装。 第二管芯耦合到衬底的第二表面。 第二封装层封装第二管芯。 第二再分配部分耦合到第二封装层。

公开(公告)号：US09263186B2

公开(公告)日：2016-02-16

申请号：US13785502

申请日：2013-03-05

Applicant: QUALCOMM Incorporated

Inventor： Yue Li ,  Xiaoming Chen ,  Zhongping Bao ,  Charles D. Paynter ,  Xiaonan Zhang ,  Ryan D. Lane

IPC: H01L49/02 ,  H01G2/06 ,  H01L23/50 ,  H01L23/64 ,  H01L23/00 ,  H01G4/38 ,  H01G4/40 ,  H01L23/498

CPC classification number: H01G2/06 ,  H01G4/38 ,  H01G4/40 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L24/17 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Some implementations provide a semiconductor device that includes a first substrate, a die coupled to the first substrate, and a set of solder balls coupled to the first substrate. The set of solder balls is configured to provide an electrical connection between the die and a second substrate. The semiconductor device also includes at least one decoupling capacitor coupled to the die through the first substrate. The at least one decoupling capacitor is configured to provide an electrical connection between the die and the second substrate. The at least one decoupling capacitor is coupled to the first substrate such that the at least one decoupling capacitor is positioned between the first substrate and the second substrate. In some implementations, the second substrate is a printed circuit board (PCB). In some implementations, the first substrate is a first package substrate, and the second substrate is a second package substrate.

Abstract translation: 一些实施方式提供一种半导体器件，其包括第一衬底，耦合到第一衬底的管芯和耦合到第一衬底的一组焊球。 该组焊球被配置成在管芯和第二衬底之间提供电连接。 半导体器件还包括通过第一衬底耦合到管芯的至少一个去耦电容器。 所述至少一个去耦电容器被配置为在所述管芯和所述第二衬底之间提供电连接。 所述至少一个去耦电容器耦合到所述第一衬底，使得所述至少一个去耦电容器位于所述第一衬底和所述第二衬底之间。 在一些实施方案中，第二衬底是印刷电路板（PCB）。 在一些实施方案中，第一衬底是第一封装衬底，第二衬底是第二封装衬底。

公开(公告)号：US20150124418A1

公开(公告)日：2015-05-07

申请号：US14073756

申请日：2013-11-06

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Daeik Daniel Kim ,  Xiaonan Zhang ,  Ryan David Lane ,  Jonghae Kim

IPC: H05K1/16

CPC classification number: H05K1/165 ,  H05K1/141 ,  H05K2201/10378

Abstract: An embedded layered inductor is provided that includes a first inductor layer and a second inductor layer coupled to the first inductor layer. The first inductor layer comprises a patterned metal layer that may also be patterned to form pads. The second inductor layer comprises metal deposited in a dielectric layer adjacent the patterned metal layer.

Abstract translation: 提供了一种嵌入式分层电感器，其包括耦合到第一电感器层的第一电感器层和第二电感器层。 第一电感器层包括图案化的金属层，其也可以被图案化以形成焊盘。 第二电感器层包括沉积在邻近图案化金属层的电介质层中的金属。

公开(公告)号：US10051741B2

公开(公告)日：2018-08-14

申请号：US14073756

申请日：2013-11-06

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Daeik Daniel Kim ,  Xiaonan Zhang ,  Ryan David Lane ,  Jonghae Kim

IPC: H05K1/18 ,  H05K1/16 ,  H05K1/14

Abstract: An embedded layered inductor is provided that includes a first inductor layer and a second inductor layer coupled to the first inductor layer. The first inductor layer comprises a patterned metal layer that may also be patterned to form pads. The second inductor layer comprises metal deposited in a dielectric layer adjacent the patterned metal layer.

公开(公告)号：US09362218B2

公开(公告)日：2016-06-07

申请号：US13968627

申请日：2013-08-16

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Young Kyu Song ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Chengjie Zuo ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H01L23/498 ,  H01L21/768 ,  H01L49/02 ,  H01L23/50 ,  H01L23/64 ,  H01L23/522

CPC classification number: H01L23/49827 ,  H01L21/76885 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/5222 ,  H01L23/642 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L2224/16225 ,  H01L2225/06572 ,  H01L2924/19105

Abstract: Some novel features pertain to a semiconductor device that includes a substrate, a first cavity that traverses the substrate. The first cavity is configured to be occupied by a interconnect material (e.g., solder ball). The substrate also includes a first metal layer coupled to a first side wall of the first cavity. The substrate further includes a first integrated passive device (IPD) on a first surface of the substrate, the first IPD coupled to the first metal layer. In some implementations, the substrate is a glass substrate. In some implementations, the first IPD is one of at least a capacitor, an inductor and/or a resistor. In some implementations, the semiconductor device further includes a second integrated passive device (IPD) on a second surface of the substrate. The second IPD is coupled to the first metal layer.

Abstract translation: 一些新颖的特征涉及一种半导体器件，其包括衬底，穿过衬底的第一腔体。 第一腔被配置为被互连材料（例如，焊球）占据。 衬底还包括耦合到第一腔的第一侧壁的第一金属层。 衬底还包括在衬底的第一表面上的第一集成无源器件（IPD），第一IPD耦合到第一金属层。 在一些实施方案中，基底是玻璃基底。 在一些实现中，第一IPD是至少一个电容器，电感器和/或电阻器中的一个。 在一些实施方式中，半导体器件还包括在衬底的第二表面上的第二集成无源器件（IPD）。 第二IPD耦合到第一金属层。

公开(公告)号：US20150237732A1

公开(公告)日：2015-08-20

申请号：US14200684

申请日：2014-03-07

Applicant: QUALCOMM Incorporated

Inventor： Mario Francisco Velez ,  Daeik Daniel Kim ,  Young Kyu Song ,  Xiaonan Zhang ,  Jonghae Kim ,  Changhan Hobie Yun ,  Chengjie Zuo

IPC: H05K1/18 ,  H01L21/48 ,  H05K3/40 ,  H05K1/03 ,  H05K1/16 ,  H01L23/498 ,  H05K1/11

CPC classification number: H05K1/182 ,  H01F17/0006 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L28/10 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/165 ,  H05K3/4038 ,  H05K2201/10015 ,  H05K2201/10242 ,  H05K2201/10984 ,  Y10T29/49165

Abstract: A low-profile passive-on-package is provided that includes a plurality of recesses that receive corresponding interconnects. Because of the receipt of the interconnects in the recesses, the passive-on-package has a height that is less than a sum of a thickness for the substrate and an interconnect height or diameter.

Abstract translation: 提供了一种低调无源封装，其包括接收相应互连的多个凹槽。 由于在凹槽中接收到互连，所以被动封装的高度小于衬底的厚度和互连高度或直径的总和。

公开(公告)号：US20150130021A1

公开(公告)日：2015-05-14

申请号：US14079488

申请日：2013-11-13

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Young Kyu Song ,  Xiaonan Zhang ,  Jonghae Kim

IPC: H01L49/02

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F41/041 ,  H01F2017/0053

Abstract: Some implementations provide an integrated device (e.g., semiconductor device) that includes a substrate and an inductor in the substrate. In some implementations, the inductor is a solenoid inductor. The inductor includes a set of windings. The set of windings has an inner perimeter. The set of windings includes a set of interconnects and a set of vias. The set of interconnects and the set of vias are located outside the inner perimeter of the set of windings. In some implementations, the set of windings further includes a set of capture pads. The set of interconnects is coupled to the set of vias through the set of capture pads. In some implementations, the set of windings has an outer perimeter. The set of pads is coupled to the set of interconnects such that the set of pads is at least partially outside the outer perimeter of the set of windings.

Abstract translation: 一些实施方式提供了一种集成器件（例如，半导体器件），其包括衬底中的衬底和电感器。 在一些实施方案中，电感器是螺线管电感器。 电感器包括一组绕组。 该组绕组具有内周。 该组绕组包括一组互连和一组通孔。 该组互连和一组通孔位于该组绕组的内周边之外。 在一些实施方案中，该组绕组还包括一组捕获垫。 该组互连通过一组捕获垫耦合到该组通孔。 在一些实施方式中，该组绕组具有外周边。 该组焊盘耦合到该组互连件，使得该组焊盘至少部分地位于该组绕组的外周边之外。

公开(公告)号：US20150092314A1

公开(公告)日：2015-04-02

申请号：US14039192

申请日：2013-09-27

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Young Kyu Song ,  Mario Francisco Velez ,  Jonghae Kim ,  Changhan Hobie Yun ,  Chengjie Zuo ,  Xiaonan Zhang ,  Ryan David Lane ,  Matthew Michael Nowak

IPC: H01F27/29 ,  H01F41/04 ,  H01F27/40

CPC classification number: H01F27/29 ,  H01F17/0006 ,  H01F27/40 ,  H01F2017/002 ,  H01F2017/0073 ,  Y10T29/4902

Abstract: A system includes a first connector coupled to a first surface of a substrate. The first connector enables the system to be electrically coupled to a first device external to the substrate. The system includes a second connector coupled to a second surface of the substrate. The system also includes a plurality of conductive vias extending through the substrate from the first surface to the second surface. The plurality of conductive vias surrounds the first connector and the second connector. The plurality of conductive vias is electrically coupled together to form a toroidal inductor. A first lead of the toroidal inductor is electrically coupled to the first connector. A second lead of the toroidal inductor is electrically coupled to the second connector.

Abstract translation: 系统包括耦合到衬底的第一表面的第一连接器。 第一连接器使得系统能够电耦合到衬底外部的第一器件。 该系统包括耦合到基板的第二表面的第二连接器。 该系统还包括从第一表面延伸穿过基底的多个导电通孔到第二表面。 多个导电通孔围绕第一连接器和第二连接器。 多个导电通孔电耦合在一起以形成环形电感器。 环形电感器的第一引线电耦合到第一连接器。 环形电感器的第二引线电耦合到第二连接器。