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    Layout technique for middle-end-of-line
    1.
    发明授权
    Layout technique for middle-end-of-line 有权

    公开(公告)号：US10325845B2

    公开(公告)日：2019-06-18

    申请号：US15628909

    申请日：2017-06-21

    Applicant: QUALCOMM Incorporated

    Inventor： Tin Tin Wee ,  Trilochan Sahoo ,  Sunil Sukumarapillai ,  Arun Kumar Kodigenahalli Venkateswar

    IPC: H01L23/522 ,  H01L29/78 ,  H01L27/088 ,  H01L29/417

    Abstract: In certain aspects of the disclosure, a die includes one or more fins, a gate formed over a first portion of the one or more fins, and a first source/drain contact formed over a second portion of the one or more fins, wherein the first source/drain contact includes an extended portion that does not overlap the one or more fins. The die also includes first and second metal lines formed from a first metal layer, wherein the first and second metal lines are spaced apart. The die further includes a first via connecting the first source/drain contact to the first metal line, and a second via connecting the first source/drain contact to the second metal line, wherein the second via lies within the extended portion of the first source/drain contact.

    LAYOUT TECHNIQUE FOR MIDDLE-END-OF-LINE
    2.
    发明申请
    LAYOUT TECHNIQUE FOR MIDDLE-END-OF-LINE 审中-公开

    公开(公告)号：US20180374792A1

    公开(公告)日：2018-12-27

    申请号：US15628909

    申请日：2017-06-21

    Applicant: QUALCOMM Incorporated

    Inventor： Tin Tin Wee ,  Trilochan Sahoo ,  Sunil Sukumarapillai ,  Arun Kumar Kodigenahalli Venkateswar

    IPC: H01L23/522 ,  H01L29/78 ,  H01L27/088 ,  H01L29/417

    Abstract: In certain aspects of the disclosure, a die includes one or more fins, a gate formed over a first portion of the one or more fins, and a first source/drain contact formed over a second portion of the one or more fins, wherein the first source/drain contact includes an extended portion that does not overlap the one or more fins. The die also includes first and second metal lines formed from a first metal layer, wherein the first and second metal lines are spaced apart. The die further includes a first via connecting the first source/drain contact to the first metal line, and a second via connecting the first source/drain contact to the second metal line, wherein the second via lies within the extended portion of the first source/drain contact.

    Systems and methods for wafer-level loopback test
    3.
    发明授权
    Systems and methods for wafer-level loopback test 有权

    公开(公告)号：US10114074B2

    公开(公告)日：2018-10-30

    申请号：US15955013

    申请日：2018-04-17

    Applicant: QUALCOMM Incorporated

    Inventor： Alvin Leng Sun Loke ,  Thomas Clark Bryan ,  Reza Jalilizeinali ,  Tin Tin Wee ,  Stephen Robert Knol ,  Luverne Ray Peterson

    IPC: G06F17/50 ,  G01R31/3177 ,  G01R31/3185 ,  G01R31/317

    Abstract: Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.

    Layout technique for middle-end-of-line
    5.
    发明授权
    Layout technique for middle-end-of-line 有权

    公开(公告)号：US10410965B2

    公开(公告)日：2019-09-10

    申请号：US16159042

    申请日：2018-10-12

    Applicant: QUALCOMM Incorporated

    Inventor： Tin Tin Wee ,  Trilochan Sahoo ,  Sunil Sukumarapillai ,  Arun Kumar Kodigenahalli Venkateswar

    IPC: H01L23/522 ,  H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8234

    Abstract: A die includes one or more fins, a gate formed over a first portion of the one or more fins, and a first source/drain contact formed over a second portion of the one or more fins, wherein the first source/drain contact includes an extended portion that does not overlap the one or more fins. The die also includes first and second metal lines formed from a first metal layer, wherein the first and second metal lines are spaced apart. The die further includes a first via connecting the first source/drain contact to the first metal line, and a second via connecting the first source/drain contact to the second metal line, wherein the second via lies within the extended portion of the first source/drain contact.

    Systems and methods for providing data channels at a die-to-die interface
    8.
    发明授权
    Systems and methods for providing data channels at a die-to-die interface 有权
    用于在管芯到管芯接口提供数据通道的系统和方法

    公开(公告)号：US09245870B1

    公开(公告)日：2016-01-26

    申请号：US14516763

    申请日：2014-10-17

    Applicant: QUALCOMM Incorporated

    Inventor： LuVerne Ray Peterson ,  Thomas Clark Bryan ,  Alvin Leng Sun Loke ,  Tin Tin Wee ,  Gregory Francis Lynch ,  Stephen Robert Knol

    IPC: H01L25/00 ,  H01L25/065

    CPC classification number: H01L25/065 ,  G06F1/10 ,  G06F17/5072 ,  G06F2217/62 ,  G06F2217/78 ,  H01L2924/0002 ,  H04L7/0095 ,  H01L2924/00

    Abstract: A circuit includes a first die having a first array of exposed data nodes, and a second die having a second array of exposed data nodes, wherein a given data node of the first array corresponds to a respective data node on the second array, further wherein the first array and the second array share a spatial arrangement of the data nodes, wherein the first die has data inputs and sequential logic circuits for each of the data nodes of the first array on a first side of the first array, and wherein the second die has data outputs and sequential logic circuits for each of the data nodes of the second array on a second side of the second array, the first and second sides being different.

    Abstract translation: 电路包括具有暴露的数据节点的第一阵列的第一管芯和具有暴露的数据节点的第二阵列的第二管芯，其中第一阵列的给定数据节点对应于第二阵列上的相应的数据节点，此外， 所述第一阵列和所述第二阵列共享所述数据节点的空间布置，其中所述第一裸片具有用于所述第一阵列的第一侧上的所述第一阵列的每个数据节点的数据输入和顺序逻辑电路，并且其中所述第二阵列 管芯具有用于第二阵列的第二侧上的第二阵列的每个数据节点的数据输出和顺序逻辑电路，第一和第二侧是不同的。

    Systems and methods for transition-minimized data bus inversion
    10.
    发明授权
    Systems and methods for transition-minimized data bus inversion 有权
    用于转换最小化数据总线反转的系统和方法

    公开(公告)号：US09244875B1

    公开(公告)日：2016-01-26

    申请号：US14335712

    申请日：2014-07-18

    Applicant: QUALCOMM Incorporated

    Inventor： Alvin Leng Sun Loke ,  Tin Tin Wee ,  Thomas Clark Bryan

    IPC: G06F13/00 ,  G06F13/40 ,  G06F13/42

    CPC classification number: G06F13/4072 ,  G06F13/4208

    Abstract: Circuits and methods for Data Bus Inversion (DBI) are provided. In one example, the immediately previous value of the DBI bit affects the next value of the DBI bit. Specifically, in some instances, the value of the DBI bit is held to the immediately previous value of the DBI bit to limit the total number of transitions on a data bus.

    Abstract translation: 提供了数据总线反转（DBI）的电路和方法。 在一个示例中，DBI位的紧接之前的值会影响DBI位的下一个值。 具体地说，在某些情况下，DBI位的值被保持到DBI位的紧前一个值，以限制数据总线上的转换总数。

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