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公开(公告)号：US09705544B2
公开(公告)日：2017-07-11
申请号：US15135653
申请日：2016-04-22
Applicant: NXP B.V.
Inventor： Remco van de Beek , Jos Verlinden
CPC classification number: H04B1/12 , H04B1/40 , H04L27/06 , H04L27/066
Abstract: A receiver and method for a wireless signal transmission system use digital amplitude modulation of a base band signal having a symbol clock frequency. The receiver includes a reference generator which generates a local reference frequency, a mixer to extract the base band signal, a high pass filter to suppress a DC component, an amplifier, an analog-to-digital converter and a digital signal processor to receive digital signals and extract symbols. A base band signal rotation detection circuit detects rotation of the base band signal upstream of the high pass filter. The digital signal processor determines a symbol clock phase by generating a coarse estimate of the symbol clock phase and correcting the coarse estimate based on detected rotations of the base band signal. A determination that the symbol clock phase corresponds to a complete rotation is used in relation to the extraction of symbols.
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公开(公告)号：US20140145787A1
公开(公告)日：2014-05-29
申请号：US13684886
申请日：2012-11-26
Applicant: NXP B.V.
Inventor： Jos Verlinden , Remco van de Beek , Massimo Ciacci
CPC classification number: H03G1/04 , H03F3/005 , H03F3/189 , H03F3/211 , H03F3/2175 , H03F3/245 , H03F3/68 , H03M1/662 , H03M1/804
Abstract: Signals are processed to facilitate the mitigation and/or cancellation of undesirable components within the signal. As consistent with one or more embodiments, input/delay circuits offset the phase of an input signal, as presented to respective amplifiers. The phase offset is used, upon combination of the outputs of the respective amplifiers, to cancel the undesirable components of the signal. Such an approach may, for example, involve phase offset in a digital domain, with correction upon combination of the signals as presented in an analog domain.
Abstract translation: 对信号进行处理以便于消除和/或消除信号内不期望的组件。 与一个或多个实施例一致，输入/延迟电路将输入信号的相位偏移到相应的放大器。 在相应放大器的输出组合时，使用相位偏移来消除信号的不期望的分量。 例如，这种方法可以涉及在数字域中的相位偏移，并且在模拟域中呈现的信号的组合进行校正。
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公开(公告)号：US11742834B2
公开(公告)日：2023-08-29
申请号：US17931867
申请日：2022-09-13
Applicant: NXP B.V.
Inventor： Sander Derksen , Jos Verlinden , Ids Christiaan Keekstra , René Verlinden
IPC: H03K3/0231 , H03K3/011
CPC classification number: H03K3/011 , H03K3/0231
Abstract: Various embodiments relate to a free running oscillator, that includes a switch capacitor based frequency-to-voltage converter (F2V), a comparator, and a voltage controlled oscillator (VCO), which may be collectively configured to reduce amplifier offset and flicker noise while increasing effective gain of the amplifier of the comparator. The F2V may produce a feedback voltage Vfb corresponding to frequencies of output of the VCO. The comparator may be configured to sample a reference voltage Vref using a sampling capacitor, compare Vref to Vfb, and generate an output based on any difference between Vref and Vfb, where the output may be integrated using an integrating capacitor of the comparator. The comparator may compensate for parasitic capacitance at the output of the amplifier by using an amplifier having two outputs, with the sampling capacitor and integrating capacitor being coupled to respectively different outputs of the amplifier.
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公开(公告)号：US20230006655A1
公开(公告)日：2023-01-05
申请号：US17931867
申请日：2022-09-13
Applicant: NXP B.V.
Inventor： Sander Derksen , Jos Verlinden , Ids Christiaan Keekstra , René Verlinden
IPC: H03K3/011 , H03K3/0231
Abstract: Various embodiments relate to a free running oscillator, that includes a switch capacitor based frequency-to-voltage converter (F2V), a comparator, and a voltage controlled oscillator (VCO), which may be collectively configured to reduce amplifier offset and flicker noise while increasing effective gain of the amplifier of the comparator. The F2V may produce a feedback voltage Vfb corresponding to frequencies of output of the VCO. The comparator may be configured to sample a reference voltage Vref using a sampling capacitor, compare Vref to Vfb, and generate an output based on any difference between Vref and Vfb, where the output may be integrated using an integrating capacitor of the comparator. The comparator may compensate for parasitic capacitance at the output of the amplifier by using an amplifier having two outputs, with the sampling capacitor and integrating capacitor being coupled to respectively different outputs of the amplifier.
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公开(公告)号：US10250266B2
公开(公告)日：2019-04-02
申请号：US15657250
申请日：2017-07-24
Applicant: NXP B.V.
Inventor： Anne-Johan Annema , Jos Verlinden
IPC: H03L7/083
Abstract: An oscillator system for an integrated circuit includes a first oscillator circuit, a second oscillator circuit, and calibration system. During a sampling routine, the calibration system is used to determine a sampled value based on a comparison of the output of the second oscillator and an external clock signal. The sampled value is stored in a memory. During a calibration routine, the calibration system determines a comparison value based on a comparison of the output of the second oscillator circuit and the output of the first oscillator circuit. The calibration circuit compares the comparison value with the sampled value to generate a tuning value to tune the frequency of the first oscillator circuit.
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Patent Agency Ranking
公开(公告)号：US20160315646A1
公开(公告)日：2016-10-27
申请号：US15135653
申请日：2016-04-22
Applicant: NXP B.V.
Inventor： Remco van de Beek , Jos Verlinden
CPC classification number: H04B1/12 , H04B1/40 , H04L27/06 , H04L27/066
Abstract: A receiver and method for a wireless signal transmission system use digital amplitude modulation of a base band signal having a symbol clock frequency. The receiver includes a reference generator which generates a local reference frequency, a mixer to extract the base band signal, a high pass filter to suppress a DC component, an amplifier, an analogue-to-digital converter and a digital signal processor to receive digital signals and extract symbols. A base band signal rotation detection circuit detects rotation of the base band signal upstream of the high pass filter. The digital signal processor determines a symbol clock phase by generating a coarse estimate of the symbol clock phase and correcting the coarse estimate based on detected rotations of the base band signal. A determination that the symbol clock phase corresponds to a complete rotation is used in relation to the extraction of symbols.
Abstract translation: 用于无线信号传输系统的接收机和方法使用具有符号时钟频率的基带信号的数字幅度调制。 接收机包括产生本地参考频率的参考发生器，提取基带信号的混频器，抑制直流分量的高通滤波器，放大器，模拟数字转换器和数字信号处理器以接收数字 信号和提取符号。 基带信号旋转检测电路检测高通滤波器上游的基带信号的旋转。 数字信号处理器通过生成符号时钟相位的粗略估计并基于检测到的基带信号的旋转来校正粗略估计来确定符号时钟相位。 符号时钟相位对应于完整旋转的确定用于符号提取。
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公开(公告)号：US20160294541A1
公开(公告)日：2016-10-06
申请号：US15085776
申请日：2016-03-30
Applicant: NXP B.V.
Inventor： Remco van de Beek , Jos Verlinden , Ghiath Al-kadi
CPC classification number: H04L7/033 , G06F1/0321 , H03L7/0992 , H03L7/23 , H04B5/0031 , H04L61/1552
Abstract: A digital synchronizer is disclosed, comprising: a phase locked loop (100) configured to produce an output signal (clkFc) having the same frequency as an input signal (Frx) by selecting a divider ratio (/P) of a frequency divider (130) with a control signal (Pctrl), the frequency divider (130) configured to divide the frequency of a high frequency signal (clkHF) by the divider ratio (/P) to provide the output signal (clkFc); a carrier generator (300) comprising a look-up table (320), the carrier generator (300) configured to generate an oversampled carrier signal using the look-up-table (320) by using the control signal (Pctrl) to produce a carrier signal with a period corresponding with a contemporaneous period of the output signal (clkFc).
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公开(公告)号：US20160294398A1
公开(公告)日：2016-10-06
申请号：US15085821
申请日：2016-03-30
Applicant: NXP B.V.
Inventor： Jos Verlinden , Remco van de Beek , Stefan Mendel
CPC classification number: H03L7/087 , H03L7/1075 , H03L7/1803 , H03L7/197 , H03L7/1974 , H03L7/235 , H04B5/0031 , H04L7/0331 , H04W4/80
Abstract: Apparatus for clock synchronisation comprising a first phase locked loop (405) and a second phase locked loop (400). The first phase locked loop (405) is configured to receive a reference signal (Fcrystal) having a reference frequency, and operable to produce an output signal (Fout) having an output frequency that is a multiple of the reference frequency. The first phase locked loop (405) comprises a frequency divider (428) that controls the multiple in response to a control signal. The second phase locked loop (400) is configured to determine a phase error between the output signal (Fout) and an input signal (Fantenna), and to provide the control signal to the first phase locked loop (405). The second phase locked loop (400) comprises phase adjustment means (450), operable to adjust a phase difference between the input and output signal by varying the control signal for a duration.
Abstract translation: 用于时钟同步的装置包括第一锁相环（405）和第二锁相环（400）。 第一锁相环（405）被配置为接收具有参考频率的参考信号（Fcrystal），并且可操作以产生具有作为参考频率倍数的输出频率的输出信号（Fout）。 第一锁相环（405）包括响应于控制信号来控制多个的分频器（428）。 第二锁相环（400）被配置为确定输出信号（Fout）和输入信号（Fantenna）之间的相位误差，并将控制信号提供给第一锁相环（405）。 第二锁相环（400）包括相位调整装置（450），可操作以通过在一段持续时间内改变控制信号来调节输入和输出信号之间的相位差。
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公开(公告)号：US08842720B2
公开(公告)日：2014-09-23
申请号：US13929670
申请日：2013-06-27
Applicant: NXP B.V.
Inventor： Remco Cornelis Herman van de Beek , Massimo Ciacci , Jos Verlinden , Ghaith Al-kadi
CPC classification number: H04L25/03891 , H03F1/3241 , H03F3/195 , H03F3/24 , H04L25/03343 , H04L25/49 , H04L27/368
Abstract: The method comprises receiving an input stream of symbols (x(i)) representing a phase change and magnitude of an RF signal, the magnitudes of the symbols are constant, the phase changes of the symbols encode digital information, and adjust the input stream of symbols to reduce inter-symbol interference. The adjusting iteratively determines a next symbol of the equalized stream (x′(n)) after receiving a next symbol of the input stream (x(n)) by multiplying the next symbol of the input stream (x(n)) with a next adjusting real number (a(n)), multiplying a previous symbol of the input stream (x(n−1)) with a previous adjusting real number (a(n−1)), the previous symbol being received before the next symbol of the input stream, and the next symbol of the equalized stream is computed from the multiplied next symbol and the multiplied previous symbol of the input stream.
Abstract translation: 该方法包括接收表示RF信号的相位变化和幅度的符号（x（i））的输入流，符号的大小是恒定的，符号的相位变化对数字信息进行编码，并且调整输入流 符号以减少符号间干扰。 在通过将输入流（x（n））的下一个符号乘以输入流（x（n））的下一个符号之后，通过将输入流（x（n））的下一个符号与 下一个调整实数（a（n）），将输入流的先前符号（x（n-1））与先前的调整实数（a（n-1））相乘），先前的符号在下一个 输入流的符号，并且均衡流的下一个符号从乘法的下一个符号和输入流的相乘的先前符号计算。
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公开(公告)号：US11783990B1
公开(公告)日：2023-10-10
申请号：US17657173
申请日：2022-03-30
Applicant: NXP B.V.
Inventor： Thomas Jan Hoen , Yanyu Jin , Anne Johan Annema , Jos Verlinden
CPC classification number: H01F27/2804 , H01F17/0006 , H01F27/29 , H01L28/10 , H03B5/12 , H01F2017/0046 , H01F2017/0073
Abstract: In an embodiment, an integrated circuit die includes a semiconductor substrate, patterned metal layers compiled over the semiconductor substrate, and a tapered multipath inductor formed in the patterned metal layers. The tapered multipath inductor includes, in turn, an inductor input terminal, an inductor output terminal, and N number of parallel inductor tracks electrically coupled between the inductor input terminal and the inductor output terminal. The parallel inductor tracks wind or wrap around an inductor centerline to define a plurality of multipath inductor windings including an innermost winding and an outermost winding. The parallel inductor tracks further vary in track width when progressing from the outermost winding to the innermost winding of the plurality of multipath inductor windings.
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