公开(公告)号：US20190212770A1

公开(公告)日：2019-07-11

申请号：US15867943

申请日：2018-01-11

Applicant: NXP B.V.

Inventor： Hamidreza Hashempour ,  Jos Verlinden ,  Ids Christiaan Keekstra

IPC: G06F1/12 ,  H03K3/037 ,  H03K5/26

CPC classification number: G06F1/12 ,  H03K3/017 ,  H03K3/037 ,  H03K5/13 ,  H03K5/26 ,  H03K2005/00019

Abstract: A clock delay circuit includes an output to provide an output clock signal which is a delayed version of an input clock signal. The clock delay circuit includes a latch whose output provides the output clock signal. A delay control circuit provides a third clock signal. The latch includes a first input to receive the input clock signal and a second input to receive the third clock signal. The amount of delay provided by the latch is dependent upon the duty cycle of the third clock signal.

公开(公告)号：US11476838B1

公开(公告)日：2022-10-18

申请号：US17362353

申请日：2021-06-29

Applicant: NXP B.V.

Inventor： Sander Derksen ,  Jos Verlinden ,  Ids Christiaan Keekstra ,  Rene Verlinden

IPC: H03K3/0231 ,  H03K3/011

Abstract: Various embodiments relate to a free running oscillator, including: a voltage controlled oscillator circuit including an input configured to receive an input voltage and an output configured to provide an oscillation signal, wherein the input voltage controls a frequency of the oscillation signal; a frequency to voltage circuit including an input configured to receive the oscillation signal and an output configured to produce a voltage dependent on a frequency of the oscillation signal; a comparison circuit including an input and an output comprising: a first amplifier including a first input, a second input, and an output, wherein the output is based upon a difference in voltage between the first input and the second input, wherein the first input received one of a reference voltage and the output of frequency to voltage circuit; a second amplifier including a first input, a second input, and an output, wherein the output is based upon a difference in voltage between the first input and the second input, first input is connected to the comparator output, the second inputs is connected to the second amplifier output; a sampling capacitor connected between the second input of the first amplifier and a ground; and an integration capacitor connected between the comparator output and the ground.

公开(公告)号：US11226649B2

公开(公告)日：2022-01-18

申请号：US15867943

申请日：2018-01-11

Applicant: NXP B.V.

Inventor： Hamidreza Hashempour ,  Jos Verlinden ,  Ids Christiaan Keekstra

IPC: G06F1/12 ,  H03K5/26 ,  H03K3/037 ,  H03K3/017 ,  H03K5/13 ,  H03K5/00

Abstract: A clock delay circuit includes an output to provide an output clock signal which is a delayed version of an input clock signal. The clock delay circuit includes a latch whose output provides the output clock signal. A delay control circuit provides a third clock signal. The latch includes a first input to receive the input clock signal and a second input to receive the third clock signal. The amount of delay provided by the latch is dependent upon the duty cycle of the third clock signal.

公开(公告)号：US11742834B2

公开(公告)日：2023-08-29

申请号：US17931867

申请日：2022-09-13

Applicant: NXP B.V.

Inventor： Sander Derksen ,  Jos Verlinden ,  Ids Christiaan Keekstra ,  René Verlinden

IPC: H03K3/0231 ,  H03K3/011

CPC classification number: H03K3/011 ,  H03K3/0231

Abstract: Various embodiments relate to a free running oscillator, that includes a switch capacitor based frequency-to-voltage converter (F2V), a comparator, and a voltage controlled oscillator (VCO), which may be collectively configured to reduce amplifier offset and flicker noise while increasing effective gain of the amplifier of the comparator. The F2V may produce a feedback voltage Vfb corresponding to frequencies of output of the VCO. The comparator may be configured to sample a reference voltage Vref using a sampling capacitor, compare Vref to Vfb, and generate an output based on any difference between Vref and Vfb, where the output may be integrated using an integrating capacitor of the comparator. The comparator may compensate for parasitic capacitance at the output of the amplifier by using an amplifier having two outputs, with the sampling capacitor and integrating capacitor being coupled to respectively different outputs of the amplifier.

公开(公告)号：US20230006655A1

公开(公告)日：2023-01-05

申请号：US17931867

申请日：2022-09-13

Applicant: NXP B.V.

Inventor： Sander Derksen ,  Jos Verlinden ,  Ids Christiaan Keekstra ,  René Verlinden

IPC: H03K3/011 ,  H03K3/0231

Abstract: Various embodiments relate to a free running oscillator, that includes a switch capacitor based frequency-to-voltage converter (F2V), a comparator, and a voltage controlled oscillator (VCO), which may be collectively configured to reduce amplifier offset and flicker noise while increasing effective gain of the amplifier of the comparator. The F2V may produce a feedback voltage Vfb corresponding to frequencies of output of the VCO. The comparator may be configured to sample a reference voltage Vref using a sampling capacitor, compare Vref to Vfb, and generate an output based on any difference between Vref and Vfb, where the output may be integrated using an integrating capacitor of the comparator. The comparator may compensate for parasitic capacitance at the output of the amplifier by using an amplifier having two outputs, with the sampling capacitor and integrating capacitor being coupled to respectively different outputs of the amplifier.