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公开(公告)号：US11431292B2
公开(公告)日：2022-08-30
申请号：US17451262
申请日：2021-10-18
Applicant: NXP B.V.
Inventor： Jos Verlinden , Rehan Ahmed , Reinier Hoogendoorn
Abstract: A circuit and method for starting-up a crystal oscillator is described. A crystal resonator is configured to be coupled to a start-up circuit including an H-bridge circuit having a number of switches. A plurality of switch control signals are generated in response to detecting a zero-crossing event of the motional current in the crystal resonator. The switches of the H-bridge circuit are controlled by the switch control signals to apply a voltage to the terminals of the crystal resonator in a first polarity during a first switch control phase and a second opposite polarity during a second switch control phase. During a respective first subphase of the respective switch control phase, the plurality of switches are configured in a first configuration to couple the supply node to a respective crystal resonator terminal. During a respective second subphase of the respective switch control phase the plurality of switches are configured in a second configuration to couple the supply node to the respective crystal resonator terminal. The resistance between the supply node and the respective crystal resonator terminal is larger in the second configuration than the first configuration. A zero-crossing is detected during each respective second sub-phase.
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公开(公告)号：US20150063517A1
公开(公告)日：2015-03-05
申请号：US14015197
申请日：2013-08-30
Applicant: NXP B.V.
Inventor： Jos Verlinden , Remco Cornelis Herman van de Beek
CPC classification number: H04L7/0331 , H03L7/0992 , H03L7/14 , H03L7/23 , H03L7/235 , H04L7/0079
Abstract: Various aspects of the present disclosure are directed apparatuses and methods including a first phase locked loop (PLL) circuit and a second PLL circuit. The first PLL circuit receives a carrier signal that is transmitted over a communications channel from a non-synchronous device, and generates a PLL-PLL control signal. The second PLL circuit receives a stable reference-oscillation signal, and, in response to the PLL-PLL control signal indicating a frequency offset, adjusts a fractional divider ratio of the second PLL circuit. The first PLL circuit and the second PLL circuit are configured to produce an output frequency signal that is synchronous to the carrier signal.
Abstract translation: 本公开的各个方面涉及包括第一锁相环（PLL）电路和第二PLL电路的装置和方法。 第一PLL电路从非同步装置接收通过通信信道发送的载波信号，并生成PLL-PLL控制信号。 第二PLL电路接收稳定的参考振荡信号，响应于指示频率偏移的PLL-PLL控制信号，调整第二PLL电路的分数除数比。 第一PLL电路和第二PLL电路被配置为产生与载波信号同步的输出频率信号。
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公开(公告)号：US08928401B2
公开(公告)日：2015-01-06
申请号：US13684886
申请日：2012-11-26
Applicant: NXP B.V.
Inventor： Jos Verlinden , Remco van de Beek , Massimo Ciacci
IPC: H03G1/04 , H03F3/68 , H03F3/217 , H03M1/66 , H03F3/00 , H03F3/21 , H03F3/24 , H03F3/189 , H03M1/80
CPC classification number: H03G1/04 , H03F3/005 , H03F3/189 , H03F3/211 , H03F3/2175 , H03F3/245 , H03F3/68 , H03M1/662 , H03M1/804
Abstract: Signals are processed to facilitate the mitigation and/or cancellation of undesirable components within the signal. As consistent with one or more embodiments, input/delay circuits offset the phase of an input signal, as presented to respective amplifiers. The phase offset is used, upon combination of the outputs of the respective amplifiers, to cancel the undesirable components of the signal. Such an approach may, for example, involve phase offset in a digital domain, with correction upon combination of the signals as presented in an analog domain.
Abstract translation: 对信号进行处理以便于消除和/或消除信号内不期望的组件。 与一个或多个实施例一致，输入/延迟电路将输入信号的相位偏移到相应的放大器。 在相应放大器的输出组合时，使用相位偏移来消除信号的不期望的分量。 例如，这种方法可以涉及在数字域中的相位偏移，并且在模拟域中呈现的信号的组合进行校正。
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公开(公告)号：US11476838B1
公开(公告)日：2022-10-18
申请号：US17362353
申请日：2021-06-29
Applicant: NXP B.V.
Inventor： Sander Derksen , Jos Verlinden , Ids Christiaan Keekstra , Rene Verlinden
IPC: H03K3/0231 , H03K3/011
Abstract: Various embodiments relate to a free running oscillator, including: a voltage controlled oscillator circuit including an input configured to receive an input voltage and an output configured to provide an oscillation signal, wherein the input voltage controls a frequency of the oscillation signal; a frequency to voltage circuit including an input configured to receive the oscillation signal and an output configured to produce a voltage dependent on a frequency of the oscillation signal; a comparison circuit including an input and an output comprising: a first amplifier including a first input, a second input, and an output, wherein the output is based upon a difference in voltage between the first input and the second input, wherein the first input received one of a reference voltage and the output of frequency to voltage circuit; a second amplifier including a first input, a second input, and an output, wherein the output is based upon a difference in voltage between the first input and the second input, first input is connected to the comparator output, the second inputs is connected to the second amplifier output; a sampling capacitor connected between the second input of the first amplifier and a ground; and an integration capacitor connected between the comparator output and the ground.
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公开(公告)号：US20220173699A1
公开(公告)日：2022-06-02
申请号：US17451262
申请日：2021-10-18
Applicant: NXP B.V.
Inventor： Jos Verlinden , Rehan Ahmed , Reinier Hoogendoorn
Abstract: A circuit and method for starting-up a crystal oscillator is described. A crystal resonator is configured to be coupled to a start-up circuit including an H-bridge circuit having a number of switches. A plurality of switch control signals are generated in response to detecting a zero-crossing event of the motional current in the crystal resonator. The switches of the H-bridge circuit are controlled by the switch control signals to apply a voltage to the terminals of the crystal resonator in a first polarity during a first switch control phase and a second opposite polarity during a second switch control phase. During a respective first subphase of the respective switch control phase, the plurality of switches are configured in a first configuration to couple the supply node to a respective crystal resonator terminal. During a respective second subphase of the respective switch control phase the plurality of switches are configured in a second configuration to couple the supply node to the respective crystal resonator terminal. The resistance between the supply node and the respective crystal resonator terminal is larger in the second configuration than the first configuration. A zero-crossing is detected during each respective second sub-phase.
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Patent Agency Ranking
公开(公告)号：US11226649B2
公开(公告)日：2022-01-18
申请号：US15867943
申请日：2018-01-11
Applicant: NXP B.V.
Inventor： Hamidreza Hashempour , Jos Verlinden , Ids Christiaan Keekstra
Abstract: A clock delay circuit includes an output to provide an output clock signal which is a delayed version of an input clock signal. The clock delay circuit includes a latch whose output provides the output clock signal. A delay control circuit provides a third clock signal. The latch includes a first input to receive the input clock signal and a second input to receive the third clock signal. The amount of delay provided by the latch is dependent upon the duty cycle of the third clock signal.
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公开(公告)号：US09973196B2
公开(公告)日：2018-05-15
申请号：US15085821
申请日：2016-03-30
Applicant: NXP B.V.
Inventor： Jos Verlinden , Remco van de Beek , Stefan Mendel
CPC classification number: H03L7/087 , H03L7/1075 , H03L7/1803 , H03L7/197 , H03L7/1974 , H03L7/235 , H04B5/0031 , H04L7/0331 , H04W4/80
Abstract: Apparatus for clock synchronization comprising a first phase locked loop (405) and a second phase locked loop (400). The first phase locked loop (405) is configured to receive a reference signal (Fcrystal) having a reference frequency, and operable to produce an output signal (Fout) having an output frequency that is a multiple of the reference frequency. The first phase locked loop (405) comprises a frequency divider (428) that controls the multiple in response to a control signal. The second phase locked loop (400) is configured to determine a phase error between the output signal (Fout) and an input signal (Fantenna), and to provide the control signal to the first phase locked loop (405). The second phase locked loop (400) comprises phase adjustment means (450), operable to adjust a phase difference between the input and output signal by varying the control signal for a duration.
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公开(公告)号：US20230134106A1
公开(公告)日：2023-05-04
申请号：US18049029
申请日：2022-10-24
Applicant: NXP B.V.
Inventor： Alexander Sebastian Delke , Anne Johan Annema , Jos Verlinden , Bram Nauta
IPC: G01K1/022
Abstract: A temperature sensor and method of temperature sensing is described. A first reference current is provided to a dual-slope ADC during a first slope time duration of a dual-slope ADC conversion cycle. A second reference current is provided to the dual-slope ADC during a second slope time duration of the dual-slope ADC conversion cycle. A digital codeword corresponding to a ratio of the first and second reference currents is then output by the dual-slope ADC. The first and second reference current ratio is related to the temperature.
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公开(公告)号：US09876631B2
公开(公告)日：2018-01-23
申请号：US15085776
申请日：2016-03-30
Applicant: NXP B.V.
Inventor： Remco van de Beek , Jos Verlinden , Ghiath Al-kadi
CPC classification number: H04L7/033 , G06F1/0321 , H03L7/0992 , H03L7/23 , H04B5/0031 , H04L61/1552
Abstract: A digital synchronizer is disclosed with a phase locked loop and a carrier generator. The phase locked loop is configured to produce an output signal having the same frequency as an input signal by selecting a divider ratio of a frequency divider with a control signal, the frequency divider divides the frequency of a high frequency signal by the divider ratio to provide the output signal; carrier generator is configured to generate an oversampled carrier signal by using the control signal to produce a carrier signal with a period corresponding with a contemporaneous period of the output signal.
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公开(公告)号：US09768985B2
公开(公告)日：2017-09-19
申请号：US15006794
申请日：2016-01-26
Applicant: NXP B.V.
Inventor： Massimo Ciacci , Ghiath Al-kadi , Remco Cornelis Herman van de Beek , Jos Verlinden
CPC classification number: H04L25/03019 , H04L25/03343 , H04L27/34 , H04L27/368 , H04L2025/03726 , H04L2025/03802
Abstract: An apparatus includes an antenna that is configured to transmit a radio frequency signal across a transmission media having a channel response impairment. A transmission path includes an encoder circuit that encodes data on a carrier signal; and a pre-equalizer circuit that is configured to pre-distort the encoded data according to equalizer coefficients representing the channel response impairment. A first equalization path includes circuitry that generates the equalizer coefficients based upon transients resulting from a presence change event for the carrier signal. A second equalization path includes circuitry that generates the equalizer coefficients based upon knowledge of encoded data on the carrier signal. Selection circuitry selects between the first equalization path and the second equalization path.
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