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公开(公告)号：US20150318979A1
公开(公告)日：2015-11-05
申请号：US14702645
申请日：2015-05-01
申请人： NXP B.V.
CPC分类号： H04L7/0276 , H04L7/0012 , H04L7/0332 , H04L7/0334
摘要： A symbol clock recovery circuit comprising an ADC, a controllable inverter and a timing detector. A timing detector input terminal is configured to receive an ADC output signal from an ADC output terminal; a timing detector output terminal is configured to provide a digital output signal; and a first timing detector feedback terminal is configured to provide a first feedback signal to the inverter control terminal. The timing detector is configured to determine an error signal associated with the received ADC output signal, and set the first feedback signal in accordance with the error signal.
摘要翻译： 一种符号时钟恢复电路，包括ADC，可控逆变器和定时检测器。 定时检测器输入端子被配置为从ADC输出端子接收ADC输出信号; 定时检测器输出端被配置为提供数字输出信号; 并且第一定时检测器反馈端子被配置为向所述逆变器控制端子提供第一反馈信号。 定时检测器被配置为确定与接收的ADC输出信号相关联的误差信号，并且根据误差信号设置第一反馈信号。
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公开(公告)号：US08928401B2
公开(公告)日：2015-01-06
申请号：US13684886
申请日：2012-11-26
申请人： NXP B.V.
发明人： Jos Verlinden , Remco van de Beek , Massimo Ciacci
IPC分类号： H03G1/04 , H03F3/68 , H03F3/217 , H03M1/66 , H03F3/00 , H03F3/21 , H03F3/24 , H03F3/189 , H03M1/80
CPC分类号： H03G1/04 , H03F3/005 , H03F3/189 , H03F3/211 , H03F3/2175 , H03F3/245 , H03F3/68 , H03M1/662 , H03M1/804
摘要： Signals are processed to facilitate the mitigation and/or cancellation of undesirable components within the signal. As consistent with one or more embodiments, input/delay circuits offset the phase of an input signal, as presented to respective amplifiers. The phase offset is used, upon combination of the outputs of the respective amplifiers, to cancel the undesirable components of the signal. Such an approach may, for example, involve phase offset in a digital domain, with correction upon combination of the signals as presented in an analog domain.
摘要翻译： 对信号进行处理以便于消除和/或消除信号内不期望的组件。 与一个或多个实施例一致，输入/延迟电路将输入信号的相位偏移到相应的放大器。 在相应放大器的输出组合时，使用相位偏移来消除信号的不期望的分量。 例如，这种方法可以涉及在数字域中的相位偏移，并且在模拟域中呈现的信号的组合进行校正。
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公开(公告)号：US09973196B2
公开(公告)日：2018-05-15
申请号：US15085821
申请日：2016-03-30
申请人： NXP B.V.
发明人： Jos Verlinden , Remco van de Beek , Stefan Mendel
CPC分类号： H03L7/087 , H03L7/1075 , H03L7/1803 , H03L7/197 , H03L7/1974 , H03L7/235 , H04B5/0031 , H04L7/0331 , H04W4/80
摘要： Apparatus for clock synchronization comprising a first phase locked loop (405) and a second phase locked loop (400). The first phase locked loop (405) is configured to receive a reference signal (Fcrystal) having a reference frequency, and operable to produce an output signal (Fout) having an output frequency that is a multiple of the reference frequency. The first phase locked loop (405) comprises a frequency divider (428) that controls the multiple in response to a control signal. The second phase locked loop (400) is configured to determine a phase error between the output signal (Fout) and an input signal (Fantenna), and to provide the control signal to the first phase locked loop (405). The second phase locked loop (400) comprises phase adjustment means (450), operable to adjust a phase difference between the input and output signal by varying the control signal for a duration.
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公开(公告)号：US09379884B2
公开(公告)日：2016-06-28
申请号：US14702645
申请日：2015-05-01
申请人： NXP B.V.
CPC分类号： H04L7/0276 , H04L7/0012 , H04L7/0332 , H04L7/0334
摘要： A symbol clock recovery circuit comprising an ADC, a controllable inverter and a timing detector. A timing detector input terminal is configured to receive an ADC output signal from an ADC output terminal; a timing detector output terminal is configured to provide a digital output signal; and a first timing detector feedback terminal is configured to provide a first feedback signal to the inverter control terminal. The timing detector is configured to determine an error signal associated with the received ADC output signal, and set the first feedback signal in accordance with the error signal.
摘要翻译： 一种符号时钟恢复电路，包括ADC，可控逆变器和定时检测器。 定时检测器输入端子被配置为从ADC输出端子接收ADC输出信号; 定时检测器输出端被配置为提供数字输出信号; 并且第一定时检测器反馈端子被配置为向所述逆变器控制端子提供第一反馈信号。 定时检测器被配置为确定与接收的ADC输出信号相关联的误差信号，并且根据误差信号设置第一反馈信号。
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公开(公告)号：US09124393B2
公开(公告)日：2015-09-01
申请号：US14136813
申请日：2013-12-20
申请人： NXP B.V.
IPC分类号： H04B5/00 , H04L5/12 , H04L27/22 , H04L1/00 , G06K19/067 , H04L7/04 , H04L27/227 , H04L27/00
CPC分类号： H04L1/0039 , G06K19/067 , H04B5/0031 , H04B5/0062 , H04B5/0093 , H04L5/001 , H04L7/041 , H04L7/042 , H04L27/22 , H04L27/227 , H04L27/2272 , H04L27/2273 , H04L2027/0036 , H04L2027/0057 , H04L2027/0095
摘要： An apparatus for detecting the end of a communication is disclosed. The apparatus includes an interface circuit for receiving an encoded signal and a carrier signal recovery circuit coupled to an output of the interface circuit. The carrier signal recovery circuit is configured to output a carrier signal of the encoded signal and a second signal that is out of phase with the carrier signal. The apparatus also includes a decoding circuit configured to decode the encoded signal as a function of both the encoded signal and the carrier signal output by the carrier signal recovery circuit. The apparatus also includes a detection circuit configured to detect an indication of an end of a communication in the encoded signal as a function of both the encoded signal and the second signal.
摘要翻译： 公开了一种用于检测通信结束的装置。 该装置包括用于接收编码信号的接口电路和耦合到接口电路的输出的载波信号恢复电路。 载波信号恢复电路被配置为输出编码信号的载波信号和与载波信号异相的第二信号。 该装置还包括解码电路，其被配置为根据由载波信号恢复电路输出的编码信号和载波信号两者对编码信号进行解码。 该装置还包括检测电路，其被配置为根据编码信号和第二信号来检测编码信号中的通信结束的指示。
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公开(公告)号：US20150180608A1
公开(公告)日：2015-06-25
申请号：US14136813
申请日：2013-12-20
申请人： NXP B.V.
IPC分类号： H04L1/00 , H04L27/22 , H04L27/227 , H04B5/00
CPC分类号： H04L1/0039 , G06K19/067 , H04B5/0031 , H04B5/0062 , H04B5/0093 , H04L5/001 , H04L7/041 , H04L7/042 , H04L27/22 , H04L27/227 , H04L27/2272 , H04L27/2273 , H04L2027/0036 , H04L2027/0057 , H04L2027/0095
摘要： An apparatus for detecting the end of a communication is disclosed. The apparatus includes an interface circuit for receiving an encoded signal and a carrier signal recovery circuit coupled to an output of the interface circuit. The carrier signal recovery circuit is configured to output a carrier signal of the encoded signal and a second signal that is out of phase with the carrier signal. The apparatus also includes a decoding circuit configured to decode the encoded signal as a function of both the encoded signal and the carrier signal output by the carrier signal recovery circuit. The apparatus also includes a detection circuit configured to detect an indication of an end of a communication in the encoded signal as a function of both the encoded signal and the second signal.
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公开(公告)号：US20160315646A1
公开(公告)日：2016-10-27
申请号：US15135653
申请日：2016-04-22
申请人： NXP B.V.
发明人： Remco van de Beek , Jos Verlinden
CPC分类号： H04B1/12 , H04B1/40 , H04L27/06 , H04L27/066
摘要： A receiver and method for a wireless signal transmission system use digital amplitude modulation of a base band signal having a symbol clock frequency. The receiver includes a reference generator which generates a local reference frequency, a mixer to extract the base band signal, a high pass filter to suppress a DC component, an amplifier, an analogue-to-digital converter and a digital signal processor to receive digital signals and extract symbols. A base band signal rotation detection circuit detects rotation of the base band signal upstream of the high pass filter. The digital signal processor determines a symbol clock phase by generating a coarse estimate of the symbol clock phase and correcting the coarse estimate based on detected rotations of the base band signal. A determination that the symbol clock phase corresponds to a complete rotation is used in relation to the extraction of symbols.
摘要翻译： 用于无线信号传输系统的接收机和方法使用具有符号时钟频率的基带信号的数字幅度调制。 接收机包括产生本地参考频率的参考发生器，提取基带信号的混频器，抑制直流分量的高通滤波器，放大器，模拟数字转换器和数字信号处理器以接收数字 信号和提取符号。 基带信号旋转检测电路检测高通滤波器上游的基带信号的旋转。 数字信号处理器通过生成符号时钟相位的粗略估计并基于检测到的基带信号的旋转来校正粗略估计来确定符号时钟相位。 符号时钟相位对应于完整旋转的确定用于符号提取。
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公开(公告)号：US20160294541A1
公开(公告)日：2016-10-06
申请号：US15085776
申请日：2016-03-30
申请人： NXP B.V.
发明人： Remco van de Beek , Jos Verlinden , Ghiath Al-kadi
CPC分类号： H04L7/033 , G06F1/0321 , H03L7/0992 , H03L7/23 , H04B5/0031 , H04L61/1552
摘要： A digital synchronizer is disclosed, comprising: a phase locked loop (100) configured to produce an output signal (clkFc) having the same frequency as an input signal (Frx) by selecting a divider ratio (/P) of a frequency divider (130) with a control signal (Pctrl), the frequency divider (130) configured to divide the frequency of a high frequency signal (clkHF) by the divider ratio (/P) to provide the output signal (clkFc); a carrier generator (300) comprising a look-up table (320), the carrier generator (300) configured to generate an oversampled carrier signal using the look-up-table (320) by using the control signal (Pctrl) to produce a carrier signal with a period corresponding with a contemporaneous period of the output signal (clkFc).
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公开(公告)号：US20160294398A1
公开(公告)日：2016-10-06
申请号：US15085821
申请日：2016-03-30
申请人： NXP B.V.
发明人： Jos Verlinden , Remco van de Beek , Stefan Mendel
CPC分类号： H03L7/087 , H03L7/1075 , H03L7/1803 , H03L7/197 , H03L7/1974 , H03L7/235 , H04B5/0031 , H04L7/0331 , H04W4/80
摘要： Apparatus for clock synchronisation comprising a first phase locked loop (405) and a second phase locked loop (400). The first phase locked loop (405) is configured to receive a reference signal (Fcrystal) having a reference frequency, and operable to produce an output signal (Fout) having an output frequency that is a multiple of the reference frequency. The first phase locked loop (405) comprises a frequency divider (428) that controls the multiple in response to a control signal. The second phase locked loop (400) is configured to determine a phase error between the output signal (Fout) and an input signal (Fantenna), and to provide the control signal to the first phase locked loop (405). The second phase locked loop (400) comprises phase adjustment means (450), operable to adjust a phase difference between the input and output signal by varying the control signal for a duration.
摘要翻译： 用于时钟同步的装置包括第一锁相环（405）和第二锁相环（400）。 第一锁相环（405）被配置为接收具有参考频率的参考信号（Fcrystal），并且可操作以产生具有作为参考频率倍数的输出频率的输出信号（Fout）。 第一锁相环（405）包括响应于控制信号来控制多个的分频器（428）。 第二锁相环（400）被配置为确定输出信号（Fout）和输入信号（Fantenna）之间的相位误差，并将控制信号提供给第一锁相环（405）。 第二锁相环（400）包括相位调整装置（450），可操作以通过在一段持续时间内改变控制信号来调节输入和输出信号之间的相位差。
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公开(公告)号：US09876631B2
公开(公告)日：2018-01-23
申请号：US15085776
申请日：2016-03-30
申请人： NXP B.V.
发明人： Remco van de Beek , Jos Verlinden , Ghiath Al-kadi
CPC分类号： H04L7/033 , G06F1/0321 , H03L7/0992 , H03L7/23 , H04B5/0031 , H04L61/1552
摘要： A digital synchronizer is disclosed with a phase locked loop and a carrier generator. The phase locked loop is configured to produce an output signal having the same frequency as an input signal by selecting a divider ratio of a frequency divider with a control signal, the frequency divider divides the frequency of a high frequency signal by the divider ratio to provide the output signal; carrier generator is configured to generate an oversampled carrier signal by using the control signal to produce a carrier signal with a period corresponding with a contemporaneous period of the output signal.
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