公开(公告)号：US11424350B2

公开(公告)日：2022-08-23

申请号：US17109897

申请日：2020-12-02

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Shigeki Koya ,  Isao Obu

IPC: H01L29/737 ,  H01L29/66 ,  H01L29/08 ,  H01L29/205

Abstract: A collector layer of an HBT includes a high-concentration collector layer and a low-concentration collector layer thereon. The low-concentration collector layer includes a graded collector layer in which the energy band gap varies to narrow with increasing distance from the base layer. The electron affinity of the semiconductor material for the base layer is greater than that of the semiconductor material for the graded collector layer at the point of the largest energy band gap by about 0.15 eV or less. The electron velocity in the graded collector layer peaks at a certain electric field strength. In the graded collector layer, the strength of the quasi-electric field, an electric field that acts on electrons as a result of the varying energy band gap, is between about 0.3 times and about 1.8 times the peak electric field strength, the electric field strength at which the electron velocity peaks.

公开(公告)号：US11329146B2

公开(公告)日：2022-05-10

申请号：US17386462

申请日：2021-07-27

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Isao Obu ,  Kaoru Ideno ,  Shigeki Koya

IPC: H01L29/737 ,  H01L29/417 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06

Abstract: A collector layer, a base layer, and an emitter layer that are disposed on a substrate form a bipolar transistor. An emitter electrode is in ohmic contact with the emitter layer. The emitter layer has a shape that is long in one direction in plan view. A difference in dimension with respect to a longitudinal direction of the emitter layer between the emitter layer and an ohmic contact interface at which the emitter layer and the emitter electrode are in ohmic contact with each other is larger than a difference in dimension with respect to a width direction of the emitter layer between the emitter layer and the ohmic contact interface.

公开(公告)号：US11276689B2

公开(公告)日：2022-03-15

申请号：US16820441

申请日：2020-03-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenji Sasaki ,  Masao Kondo ,  Shigeki Koya ,  Shinnosuke Takahashi ,  Yasunari Umemoto ,  Isao Obu ,  Takayuki Tsutsui

IPC: H03F3/187 ,  H01L27/082 ,  H01L29/737 ,  H03F3/213 ,  H03F3/195

Abstract: A semiconductor device includes two cell rows, each of which is formed of a plurality of transistor cells aligned in parallel to each other. Each of the plurality of transistor cells includes a collector region, a base region, and an emitter region that are disposed above a substrate. A plurality of collector extended wiring lines are each connected to the collector region of a corresponding one of the plurality of transistor cells and are extended in a direction intersecting an alignment direction of the plurality of transistor cells. A collector integrated wiring line connects the plurality of collector extended wiring lines to each other. A collector intermediate integrated wiring line that is disposed between the two cell rows in plan view connects the plurality of collector extended wring lines extended from the plurality of transistor cells that belong to one of the two cell rows to each other.

公开(公告)号：US10665704B2

公开(公告)日：2020-05-26

申请号：US16125234

申请日：2018-09-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao Obu ,  Yasunari Umemoto ,  Masahiro Shibata ,  Shigeki Koya ,  Masao Kondo ,  Takayuki Tsutsui

IPC: H01L29/737 ,  H01L23/00 ,  H03F3/24 ,  H03F1/56 ,  H01L29/205 ,  H03F3/195 ,  H03F3/213 ,  H01L21/308 ,  H01L21/311 ,  H01L21/285 ,  H01L21/02 ,  H01L21/306 ,  H01L29/423 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10 ,  H03F1/30 ,  H01L29/45 ,  H01L29/735 ,  H01L27/102 ,  H01L29/66 ,  H03F3/21

Abstract: A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.

公开(公告)号：US10374071B2

公开(公告)日：2019-08-06

申请号：US15598456

申请日：2017-05-18

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Yasunari Umemoto ,  Shigeki Koya ,  Shigeru Yoshida ,  Isao Obu

IPC: H01L29/66 ,  H01L29/73 ,  H01L29/737 ,  H01L29/02 ,  H01L31/109 ,  H01L29/36 ,  H01L31/072 ,  H01L29/08 ,  H01L29/15 ,  H01L21/02 ,  H01L21/331

Abstract: A heterojunction bipolar transistor includes a collector layer, a base layer, an emitter layer, and a semiconductor layer that are laminated in this order, wherein the emitter layer includes a first region having an upper surface on which the semiconductor layer is laminated, and a second region being adjacent to the first region and having an upper surface that is exposed, and the first and second regions of the emitter layer have higher doping concentrations in portions near the upper surfaces than in portions near an interface between the emitter layer and the base layer.

公开(公告)号：US10056476B1

公开(公告)日：2018-08-21

申请号：US15898440

申请日：2018-02-17

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Shigeki Koya ,  Isao Obu

IPC: H01L29/737 ,  H01L29/205 ,  H01L29/66 ,  H01L29/08

Abstract: A collector layer of an HBT includes a high-concentration collector layer and a low-concentration collector layer thereon. The low-concentration collector layer includes a graded collector layer in which the energy band gap varies to narrow with increasing distance from the base layer. The electron affinity of the semiconductor material for the base layer is greater than that of the semiconductor material for the graded collector layer at the point of the largest energy band gap by about 0.15 eV or less. The electron velocity in the graded collector layer peaks at a certain electric field strength. In the graded collector layer, the strength of the quasi-electric field, an electric field that acts on electrons as a result of the varying energy band gap, is between about 0.3 times and about 1.8 times the peak electric field strength, the electric field strength at which the electron velocity peaks.

公开(公告)号：US12009359B2

公开(公告)日：2024-06-11

申请号：US17504269

申请日：2021-10-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shinnosuke Takahashi ,  Masayuki Aoike ,  Takayuki Tsutsui ,  Shigeki Koya

IPC: H01L25/065 ,  H01L25/00 ,  H01L25/16 ,  H01L25/18 ,  H01L27/02 ,  H01L27/06 ,  H01L23/00

CPC classification number: H01L27/0658 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0255 ,  H01L24/05 ,  H01L24/13 ,  H01L24/24 ,  H01L2224/05644 ,  H01L2224/08 ,  H01L2224/08145 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/24146

Abstract: A semiconductor having transistors arranged side by side in one direction over a surface of a substrate and are connected in parallel. At least one passive element is disposed on at least one of regions between two adjacent ones of the transistors. The transistors each include a collector layer over the substrate, a base layer on the collector layer, and an emitter layer on the base layer. Collector electrodes are arranged in such a manner that each of the collector electrodes is located between the substrate and the collector layer of the corresponding one of the transistors and is electrically connected to the collector layer.

公开(公告)号：US11990873B2

公开(公告)日：2024-05-21

申请号：US17168904

申请日：2021-02-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Shaojun Ma ,  Shigeki Koya

IPC: H03F1/30 ,  H03F3/19 ,  H03F3/21

CPC classification number: H03F1/302 ,  H03F3/19 ,  H03F3/211 ,  H03F2200/451

Abstract: A first amplifier circuit in a preceding stage, a second amplifier circuit in a subsequent stage, and a ground external connection terminal are disposed on a substrate. The first and second amplifier circuits each include bipolar transistors, capacitive elements for the respective bipolar transistors, and resistive elements for the respective bipolar transistors. The bipolar transistors each include separate base electrodes, that is, a first base electrode for radio frequency and a second base electrode for biasing. The bipolar transistors of the second amplifier circuit include emitter electrodes connected to the ground external connection terminal. The minimum spacing between the first base electrode and an emitter mesa layer of at least one of the bipolar transistors of the second amplifier circuit is greater than the minimum spacing between the first base electrode and am emitter mesa layer of each of the bipolar transistors of the first amplifier circuit.

公开(公告)号：US11869957B2

公开(公告)日：2024-01-09

申请号：US17398909

申请日：2021-08-10

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenji Sasaki ,  Kingo Kurotani ,  Takashi Kitahara ,  Shigeki Koya

IPC: H01L29/737 ,  H01L23/00 ,  H01L23/482 ,  H01L29/417 ,  H01L29/06 ,  H01L23/535 ,  H01L27/082 ,  H01L29/40 ,  H03F3/19

CPC classification number: H01L29/7371 ,  H01L23/4824 ,  H01L23/535 ,  H01L24/13 ,  H01L27/0823 ,  H01L29/0692 ,  H01L29/40 ,  H01L29/41708 ,  H03F3/19 ,  H01L24/05 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/1302 ,  H01L2224/13013 ,  H01L2224/16227 ,  H01L2924/13051 ,  H03F2200/408 ,  H03F2200/451

Abstract: A compound semiconductor device comprises a heterojunction bipolar transistor including a plurality of unit transistors, a capacitor electrically connected between a RF input wire and a base wire for each unit transistor of the unit transistors, and a bump electrically connected to emitters of the unit transistors. The unit transistors are arranged in a first direction. The bump is disposed above the emitters of the unit transistors while extending in the first direction. The transistors include first and second unit transistors, the respective emitters of the first and second unit transistors being disposed on first and second sides, respectively, of a second direction, perpendicular to the first direction, with respect to a center line of the bump extending in the first direction. The capacitor is not covered by the bump, and respective lengths of the respective base wires connected respectively to the first and second unit transistors are different.

公开(公告)号：US11817356B2

公开(公告)日：2023-11-14

申请号：US17559958

申请日：2021-12-22

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Shigeki Koya ,  Isao Obu ,  Kaoru Ideno

IPC: H01L29/66 ,  H01L21/8252 ,  H01L29/737 ,  H01L29/15

CPC classification number: H01L21/8252 ,  H01L29/157 ,  H01L29/66333 ,  H01L29/7371

Abstract: A collector layer, a base layer, an emitter layer, and an emitter mesa layer are placed above a substrate in this order. A base electrode and an emitter electrode are further placed above the substrate. The emitter mesa layer has a long shape in a first direction in plan view. The base electrode includes a base electrode pad portion spaced from the emitter mesa layer in the first direction. An emitter wiring line and a base wiring line are placed on the emitter electrode and the base electrode, respectively. The emitter wiring line is connected to the emitter electrode via an emitter contact hole. In the first direction, the spacing between the edges of the emitter mesa layer and the emitter contact hole on the side of the base wiring line is smaller than that between the emitter mesa layer and the base wiring line.