公开(公告)号：US11276689B2

公开(公告)日：2022-03-15

申请号：US16820441

申请日：2020-03-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenji Sasaki ,  Masao Kondo ,  Shigeki Koya ,  Shinnosuke Takahashi ,  Yasunari Umemoto ,  Isao Obu ,  Takayuki Tsutsui

IPC: H03F3/187 ,  H01L27/082 ,  H01L29/737 ,  H03F3/213 ,  H03F3/195

Abstract: A semiconductor device includes two cell rows, each of which is formed of a plurality of transistor cells aligned in parallel to each other. Each of the plurality of transistor cells includes a collector region, a base region, and an emitter region that are disposed above a substrate. A plurality of collector extended wiring lines are each connected to the collector region of a corresponding one of the plurality of transistor cells and are extended in a direction intersecting an alignment direction of the plurality of transistor cells. A collector integrated wiring line connects the plurality of collector extended wiring lines to each other. A collector intermediate integrated wiring line that is disposed between the two cell rows in plan view connects the plurality of collector extended wring lines extended from the plurality of transistor cells that belong to one of the two cell rows to each other.

公开(公告)号：US12009359B2

公开(公告)日：2024-06-11

申请号：US17504269

申请日：2021-10-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shinnosuke Takahashi ,  Masayuki Aoike ,  Takayuki Tsutsui ,  Shigeki Koya

IPC: H01L25/065 ,  H01L25/00 ,  H01L25/16 ,  H01L25/18 ,  H01L27/02 ,  H01L27/06 ,  H01L23/00

CPC classification number: H01L27/0658 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0255 ,  H01L24/05 ,  H01L24/13 ,  H01L24/24 ,  H01L2224/05644 ,  H01L2224/08 ,  H01L2224/08145 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/24146

Abstract: A semiconductor having transistors arranged side by side in one direction over a surface of a substrate and are connected in parallel. At least one passive element is disposed on at least one of regions between two adjacent ones of the transistors. The transistors each include a collector layer over the substrate, a base layer on the collector layer, and an emitter layer on the base layer. Collector electrodes are arranged in such a manner that each of the collector electrodes is located between the substrate and the collector layer of the corresponding one of the transistors and is electrically connected to the collector layer.

公开(公告)号：US11495563B2

公开(公告)日：2022-11-08

申请号：US16994187

申请日：2020-08-14

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masao Kondo ,  Kenji Sasaki ,  Shigeki Koya ,  Shinnosuke Takahashi

IPC: H01L23/00 ,  H03F1/56 ,  H03F3/20

Abstract: Two transistor rows are arranged on or in a substrate. Each of the two transistor rows is configured by a plurality of transistors aligned in a first direction, and the two transistor rows are arranged at an interval in a second direction orthogonal to the first direction. A first wiring is arranged between the two transistor rows when seen from above. The first wiring is connected to collectors or drains of the plurality of transistors in the two transistor rows. The first bump overlaps with the first wiring when seen from above, is arranged between the two transistor rows, and is connected to the first wiring.

公开(公告)号：US11139390B2

公开(公告)日：2021-10-05

申请号：US16719153

申请日：2019-12-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shinnosuke Takahashi

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/732 ,  H01L29/10

Abstract: An emitter mesa and a base electrode are arranged on a base mesa on a substrate. A base wiring line on the base electrode is connected to the base electrode via base openings. The emitter mesa includes a plurality of emitter fingers having a planar shape that is long in one direction. The emitter fingers include first and second emitter fingers. The base openings are arranged so as to be spaced apart in a longitudinal direction from first end portions of the first emitter fingers and are not arranged in a region obtained by extending the second emitter finger in the longitudinal direction. An end portion of the second emitter finger that is near the base openings protrudes in the longitudinal direction beyond the end portions of the first emitter fingers that are near the base openings.

公开(公告)号：US11876032B2

公开(公告)日：2024-01-16

申请号：US17504316

申请日：2021-10-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shinnosuke Takahashi ,  Masayuki Aoike ,  Masatoshi Hase ,  Fumio Harima

IPC: H01L23/373 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L29/737

CPC classification number: H01L23/3738 ,  H01L23/3736 ,  H01L24/08 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L24/05 ,  H01L24/24 ,  H01L29/7371 ,  H01L2224/05644 ,  H01L2224/08145 ,  H01L2224/1357 ,  H01L2224/13147 ,  H01L2224/13644 ,  H01L2224/24146

Abstract: A bond layer including at least one metal region in a plan view is disposed on a surface layer portion of a substrate formed from a semiconductor. A semiconductor element is disposed on the bond layer and includes a first transistor disposed on a first metal region that is a metal region as the at least one metal region of the bond layer and including a collector layer electrically coupled to the first metal region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer. A first emitter electrode is disposed on the emitter layer of the first transistor. A first conductor protrusion is disposed on the first emitter electrode. The thermal conductivity of the semiconductor material of the surface layer portion is higher than that of each of the collector layer, the base layer, and the emitter layer of the first transistor.

公开(公告)号：US11784245B2

公开(公告)日：2023-10-10

申请号：US17002618

申请日：2020-08-25

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenji Sasaki ,  Yasunari Umemoto ,  Shigeki Koya ,  Shinnosuke Takahashi ,  Masao Kondo

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/08 ,  H01L29/205 ,  H01L29/417 ,  H01L27/02 ,  H01L23/528 ,  H03K17/60 ,  H01L23/00 ,  H03F3/189

CPC classification number: H01L29/7371 ,  H01L23/5286 ,  H01L24/13 ,  H01L27/0229 ,  H01L29/0692 ,  H01L29/0826 ,  H01L29/205 ,  H01L29/41708 ,  H03K17/602 ,  H03F3/189 ,  H03F2200/222 ,  H03F2200/318 ,  H03F2200/387 ,  H03F2200/451

Abstract: An electrically conductive sub-collector layer is provided in a surface layer portion of a substrate. A collector layer, a base layer, and an emitter layer are located within the sub-collector layer when viewed in plan. The collector layer is connected to the sub-collector layer. An emitter electrode and a base electrode are long in a first direction when viewed in plan. The emitter electrode overlaps the emitter layer. The base electrode and the emitter electrode are discretely located away from each other in a second direction orthogonal to the first direction. A collector electrode is located on one side in the second direction with respect to the emitter electrode and is not located on the other side when viewed in plan. A base line is connected to the base electrode in a manner so as to adjoin a portion other than longitudinal ends of the base electrode.

公开(公告)号：US10396148B2

公开(公告)日：2019-08-27

申请号：US15960845

申请日：2018-04-24

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shinnosuke Takahashi ,  Masayuki Aoike

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/40 ,  H01L29/778 ,  H01L29/66 ,  H01L21/76 ,  H01L21/762 ,  H01L29/47 ,  H01L29/205

Abstract: A semiconductor layer arranged on a semiconductor substrate includes an active region and an element isolation region that surrounds the first active region when viewed in plan. A field effect transistor is formed in the active region. A plurality of guard ring electrodes separated from each other affect a potential of the active region through the element isolation region. An interlayer insulating film is formed over the semiconductor layer, the field effect transistor, and the guard ring electrodes. At least one guard ring connection wiring formed on the interlayer insulating film electrically interconnects the plurality of guard ring electrodes.