公开(公告)号：US06184565B2

公开(公告)日：2001-02-06

申请号：US09378157

申请日：1998-03-10

Applicant: James D. Beasom

Inventor： James D. Beasom

IPC: H01L2358

CPC classification number: H01L27/0229

Abstract: The reduction in breakdown voltage of a device which contains adjoining regions of relatively high and low impurity concentrations within a dielectrically isolated island of an integrated circuit architecture is effectively countered by biasing the material surrounding the island, such as a support polysilicon substrate or the fill material of a isolated trench, at a prescribed bias voltage that is insufficient to cause the avalanche-generation of electron-hole pairs in the vicinity of the relatively high-to-low impurity concentration junction between the buried layer and the island. Where a plurality of islands are supported in and surrounded by a common substrate material of an overall integrated circuit architecture, the prescribed bias voltage may be set at a value that is no more positive than half the difference between the most positive and the most negative of the bias voltages that are applied to the integrated circuit. Where respective islands do not share a common (continuously connected) substrate, the surrounding material of each island is biased at a voltage sufficiently close to the island voltage as to prevent avalanche-generation of carrier pairs; this voltage may be the same bias voltage applied to the island material itself.

Abstract translation: 通过偏置岛周围的材料，例如支撑多晶硅衬底或填充材料，可以有效地抵消在集成电路架构的介电隔离岛内包含相对高和低杂质浓度相邻区域的器件的击穿电压的降低 在规定的偏置电压下，不能在埋层和岛之间的相对高 - 低杂质浓度结的附近产生电子 - 空穴对的雪崩。 在整个集成电路结构的共同衬底材料被支撑并被其围绕的情况下，规定的偏置电压可以被设定为不大于最正和最负的 施加到集成电路的偏置电压。 在各个岛不共享公共（连续连接）的基板的情况下，每个岛的周围材料被偏置在足够接近岛电压的电压，以防止载波对的雪崩产生; 该电压可能是施加到岛材料本身的相同的偏置电压。

公开(公告)号：US4578695A

公开(公告)日：1986-03-25

申请号：US554025

申请日：1983-11-21

Applicant: Francois-Xavier Delaporte ,  Gerard M. Lebesnerais ,  Jean-Pierre Pantani

Inventor： Francois-Xavier Delaporte ,  Gerard M. Lebesnerais ,  Jean-Pierre Pantani

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/02 ,  H01L27/06 ,  H01L29/8605 ,  H03K19/0175 ,  H02H9/04 ,  H03K3/01 ,  H03K5/153

CPC classification number: H03K19/017509 ,  H01L27/0229 ,  H01L29/8605

Abstract: A monolithically integrated resistive attenuator is autobiased from an input bipolar signal the amplitude of which is higher than the integrated circuit voltage supplies. The resistive attenuator is arranged in a first pocket formed in an epitaxial layer, and is connected between the input bipolar signal and ground. An intermediate tap produces an output signal. A diode and capacitor are formed in a second pocket. The diode is connected between the input bipolar signals and the epitaxial layer while the capacitor is connected between the epitaxial layer and the isolation walls thereof. The positive half-periods of the input bipolar signal charges the capacitor, which in turn biases the epitaxial layers. The attenuator, therefore, can be monolithically integrated into a silicon chip and remain isolated for all values of the input bipolar signal. The output signal produced by the attenuator is less than the integrated circuit voltage supplies so that the circuits driven by the output signal can be integrated without difficulties.

Abstract translation: 单片集成电阻衰减器从输入双极性信号自动偏置，其幅度高于集成电路电压源。 电阻衰减器布置在形成于外延层中的第一凹坑中，并连接在输入双极性信号和地之间。 中间抽头产生输出信号。 二极管和电容器形成在第二口袋中。 二极管连接在输入双极性信号和外延层之间，而电容器连接在外延层及其隔离壁之间。 输入双极性信号的正半周期对电容器充电，电容器进一步偏置外延层。 因此，衰减器可以单片集成到硅芯片中，并且对于输入双极性信号的所有值保持隔离。 由衰减器产生的输出信号小于集成电路电压供应，使得由输出信号驱动的电路可以毫无困难地集成。

公开(公告)号：US4403240A

公开(公告)日：1983-09-06

申请号：US200459

申请日：1980-10-24

Applicant: Kunio Seki ,  Ritsuji Takeshita

Inventor： Kunio Seki ,  Ritsuji Takeshita

IPC: H01L21/822 ,  H01L21/3205 ,  H01L21/60 ,  H01L23/48 ,  H01L23/50 ,  H01L23/52 ,  H01L23/528 ,  H01L23/58 ,  H01L27/02 ,  H01L27/04

CPC classification number: H01L24/06 ,  H01L23/50 ,  H01L23/528 ,  H01L23/58 ,  H01L24/05 ,  H01L24/49 ,  H01L27/0229 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105

Abstract: A semiconductor integrated circuit device for an amplifier circuit including a semiconductor substrate in which an audio amplifier circuit is formed in an integrated circuit form, at least one first wire bonding pad which is formed on said semiconductor substrate to ground said audio amplifier circuit, and an externally connecting terminal which is provided being separated away from said semiconductor substrate and which is electrically connected to said first wire bonding pad via a metal wire, wherein the improvement comprises a wire bonding pad for the substrate which is formed on said semiconductor substrate being separated away from said first wire bonding pad, and which grounds said semiconductor substrate, and a metallic connector wire which electrically connects said wire bonding pad for the substrate to said externally connecting terminal.

Abstract translation: 一种用于放大器电路的半导体集成电路器件，包括其中以集成电路形式形成音频放大器电路的半导体衬底，形成在所述半导体衬底上以对接所述音频放大器电路的至少一个第一引线接合焊盘，以及 所述外部连接端子被设置为与所述半导体衬底分离并且经由金属线电连接到所述第一引线接合焊盘，其中所述改进包括形成在所述半导体衬底上的用于衬底的引线焊盘，所述引线焊盘被分离 从所述第一引线接合焊盘接地，并且将所述半导体衬底接地，以及将所述衬底的所述引线焊盘电连接到所述外部连接端子的金属连接器线。

公开(公告)号：US3974404A

公开(公告)日：1976-08-10

申请号：US562306

申请日：1975-03-26

Applicant: William Folsom Davis

Inventor： William Folsom Davis

IPC: G05F3/22 ,  H01L27/00 ,  H01L27/02 ,  H01L27/04 ,  H01L27/082 ,  H02H7/20 ,  H03F1/52 ,  H03H11/40 ,  H03H11/48 ,  H03K17/16

CPC classification number: H03K17/16 ,  G05F3/22 ,  H01L27/00 ,  H01L27/0214 ,  H01L27/0229 ,  H01L27/0248 ,  H01L27/04 ,  H01L27/0821 ,  H02H7/20 ,  H02H7/205 ,  H03F1/52

Abstract: An interface circuit for integrated circuit devices which prevents deleterious injection of minority carriers into the substrate during overvoltages applied to a terminal of the integrated circuit. A lateral PNP transistor formed in an N-type region has its base connected to a bias circuit and its collector connected to a load circuit and its emitter connected to a current source having a P-type electrode. The emitter is also connected to a first terminal of the integrated circuit. If the first terminal is connected to a signal wire having large negative noise pulses thereon, the emitter-base junction of the lateral PNP transistor will become reverse biased during the negative pulses, thereby preventing the injection of minority carriers into the P-type substrate in which the integrated circuit is fabricated. If the terminal is connected to a second terminal of a second integrated circuit having therein a lateral PNP transistor having its base connected to a control circuit and its collector connected to a load circuit, the first and second lateral PNP transistors and the current source form a differential amplifier, which provides a low impedance to noise impulses applied to the terminals.

Abstract translation: 一种用于集成电路器件的接口电路，其防止在施加到集成电路的端子的过电压期间有害地将少数载流子注入基板。 形成在N型区域中的横向PNP晶体管的基极连接到偏置电路，其集电极连接到负载电路，其发射极连接到具有P型电极的电流源。 发射极也连接到集成电路的第一端子。 如果第一端子连接到其上具有大的负噪声脉冲的信号线，则横向PNP晶体管的发射极 - 基极结将在负脉冲期间变为反向偏置，从而防止少数载流子注入到P型衬底中 制造集成电路。 如果端子连接到第二集成电路的第二端子，其中具有其基极连接到控制电路并且其集电极连接到负载电路的横向PNP晶体管，则第一和第二横向PNP晶体管和电流源形成 差分放大器提供了对端子施加的低阻抗噪声脉冲。

公开(公告)号：US3911296A

公开(公告)日：1975-10-07

申请号：US51275474

申请日：1974-10-07

Applicant: MOTOROLA INC

Inventor： DAVIS WILLIAM FOLSOM

IPC: F02P3/08 ,  G05F1/56 ,  G05F3/22 ,  H01L21/331 ,  H01L21/76 ,  H01L21/822 ,  H01L27/00 ,  H01L27/02 ,  H01L27/04 ,  H01L27/082 ,  H01L29/73 ,  H02H7/20 ,  H02H9/04 ,  H03F1/52 ,  H03H11/40 ,  H03H11/46 ,  H03H11/48 ,  H03K17/16 ,  H03K1/12

CPC classification number: H03K17/16 ,  B60K28/00 ,  G05F3/22 ,  H01L27/00 ,  H01L27/0214 ,  H01L27/0229 ,  H01L27/0248 ,  H01L27/04 ,  H01L27/0821 ,  H02H7/20 ,  H02H7/205 ,  H02H9/005 ,  H03F1/52 ,  H03H11/00 ,  H03H11/483

Abstract: A capacitance multiplier circuit having first and second terminals adapted for use in integrated circuits. An NPN transistor has its emitter connected to the second terminal, its base connected to one electrode of a capacitor and its collector connected to the other electrode of the capacitor and also to the first terminal. Increasing the voltage of the first terminal causes a charging current to flow in the capacitor and into the base of the transistor. The capacitor charging current is multiplied by the current gain of the transistor. The apparent capacitance between the first and second terminals is equal to the capacitance of the capacitor multiplied by the current gain of the transistor.

Abstract translation: 具有适于在集成电路中使用的第一和第二端子的电容倍增器电路。 NPN晶体管的发射极连接到第二端子，其基极连接到电容器的一个电极，其集电极连接到电容器的另一个电极，并连接到第一端子。 增加第一端子的电压使得电容器中的充电电流流入晶体管的基极。 电容充电电流乘以晶体管的电流增益。 第一和第二端子之间的视在电容等于电容器的电容乘以晶体管的电流增益。

公开(公告)号：US3525910A

公开(公告)日：1970-08-25

申请号：US3525910D

申请日：1968-05-31

Applicant: WESTINGHOUSE ELECTRIC CORP

Inventor： PHILIPS JOHN

IPC: H01L29/41 ,  H01L23/31 ,  H01L23/48 ,  H01L23/482 ,  H01L27/02 ,  H01L29/00 ,  H01L29/06 ,  H01L3/00

CPC classification number: H01L29/0657 ,  H01L23/3157 ,  H01L23/4824 ,  H01L24/72 ,  H01L27/0229 ,  H01L29/00 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/12036 ,  H01L2924/1301 ,  Y10S257/926 ,  H01L2924/00

公开(公告)号：US5072133A

公开(公告)日：1991-12-10

申请号：US692801

申请日：1991-02-20

Applicant: John A. Zoutendyk

Inventor： John A. Zoutendyk

IPC: H01L27/02 ,  H03K3/037

CPC classification number: H01L27/0229 ,  H03K3/0375

Abstract: Bipolar transistors fabricated in separate buried layers of an integrated circuit chip are electrically isolated with a built-in potential barrier established by doping the buried layer with a polarity opposite doping in the chip substrate. To increase the resistance of the bipolar transistors to single-event upsets due to ionized particle radiation, the substrate is biased relative to the buried layer with an external bias voltage selected to offset the built-in potential just enough (typically between about +0.1 to +0.2 volt) to prevent an accumulation of charge in the buried-layer-substrate junction.

Abstract translation: 制造在集成电路芯片的分开的掩埋层中的双极晶体管通过在芯片衬底中掺杂极性相反的掺杂掩埋层而建立的内置势垒电隔离。 为了将双极晶体管的电阻增加到由于电离粒子辐射引起的单事件不均匀性，衬底相对于掩埋层被偏置，其外部偏置电压被选择以足以抵消内置电位（通常在约+0.1至 +0.2伏），以防止在埋层 - 衬底结中积累电荷。

公开(公告)号：US4905067A

公开(公告)日：1990-02-27

申请号：US173213

申请日：1988-03-25

Applicant: Marco Morelli ,  Fabio Marchio ,  Francesco Tricoli ,  Giampietro Maggioni

Inventor： Marco Morelli ,  Fabio Marchio ,  Francesco Tricoli ,  Giampietro Maggioni

IPC: H01L21/8222 ,  H01L27/02 ,  H01L27/06 ,  H03K17/16 ,  H03K17/64

CPC classification number: H01L27/0229 ,  H01L27/0248 ,  H03K17/16 ,  H03K17/64

Abstract: An integrated circuit for driving inductive loads comprises at least one substrate and a plurality of separate epitaxial wells, and has at least one output terminal for connection to an inductive load and a reference terminal for connection to a reference voltage. To reliably isolate the different epitaxial wells in each operating state, the circuit comprises diodes interposed between the substrate on one side and the output and reference terminals on the other to set the substrate to the reference potential when the potential on the output terminal is greater than the reference potential and to set the substrate to the output potential when the latter becomes smaller than the reference potential.

公开(公告)号：US4039857A

公开(公告)日：1977-08-02

申请号：US566707

申请日：1975-04-10

Applicant: Adel Abdel Aziz Ahmed

Inventor： Adel Abdel Aziz Ahmed

IPC: H01L27/02 ,  H01L27/07 ,  H01L27/08 ,  H03K19/003 ,  H03K19/082 ,  H03K19/086 ,  H04Q3/52 ,  H03K19/12

CPC classification number: H01L27/0802 ,  H01L27/0229 ,  H01L27/0755 ,  H03K19/00307 ,  H03K19/082 ,  H03K19/086 ,  H04Q3/521

Abstract: A diode current steering network is fabricated in minimum area in a monolithic integrated circuit by dynamically biasing an isolation boat wherein are contained diffused resistors connected to the various circuit points to which current is to be steered.

公开(公告)号：US4005342A

公开(公告)日：1977-01-25

申请号：US524186

申请日：1974-11-15

Applicant: William Folsom Davis

Inventor： William Folsom Davis

IPC: G05F3/22 ,  H01L27/00 ,  H01L27/02 ,  H01L27/04 ,  H01L27/082 ,  H02H7/20 ,  H03F1/52 ,  H03H11/40 ,  H03H11/48 ,  H03K17/16 ,  H02H3/22

CPC classification number: H03K17/16 ,  G05F3/22 ,  H01L27/00 ,  H01L27/0214 ,  H01L27/0229 ,  H01L27/0248 ,  H01L27/04 ,  H01L27/0821 ,  H02H7/20 ,  H02H7/205 ,  H03F1/52

Abstract: An overvoltage protection circuit in an integrated circuit for increasing the breakdown voltage of the integrated circuit between first and second terminals thereof. Diode-connected transistors are connected in series between the first terminal and a resistor. The resistor is connected to the base of a first transistor having its emitter connected to the second terminal and its collector connected to the base of a second transistor having its emitter connected to the second terminal and its collector connected to the first terminal. If an overvoltage applied between the first and second terminals exceeds the sum of the emitter-base reverse breakdown voltages of the diode-connected transistors, current flows into the base of the first transistor, causing it to saturate, thereby preventing the emitter-base junction of the second transistor from being forward biased. The collector to emitter breakdown voltage of the second transistor is thereby increased.

Abstract translation: 一种集成电路中的过电压保护电路，用于增加集成电路的第一和第二端子之间的击穿电压。 二极管连接的晶体管串联在第一端子和电阻器之间。 电阻器连接到第一晶体管的基极，其第一晶体管的发射极连接到第二端子，其集电极连接到第二晶体管的基极，其第二晶体管的发射极连接到第二端子，其集电极连接到第一端子。 如果施加在第一和第二端子之间的过电压超过二极管连接的晶体管的发射极 - 反向击穿电压的总和，则电流流入第一晶体管的基极，使其饱和，从而防止发射极 - 基极结 的第二晶体管被正向偏置。 因此，第二晶体管的集电极至发射极击穿电压增加。