公开(公告)号：US07606151B2

公开(公告)日：2009-10-20

申请号：US10547143

申请日：2005-04-21

申请人： Murali S Chilukoor

发明人： Murali S Chilukoor

IPC分类号： H04L12/26

CPC分类号： H04L49/40 ,  H04Q3/521 ,  H04Q2213/13003 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/1308 ,  H04Q2213/13103 ,  H04Q2213/13214 ,  H04Q2213/13296 ,  H04Q2213/13322 ,  H04Q2213/13389

摘要： A method according to one embodiment may include receiving, by an integrated circuit of a switch, a plurality of packets, monitoring a rate of the plurality of packets received at the integrated circuit, and adjusting a power consumption of at least a part of the integrated circuit in response to the rate of the plurality of packets received at the integrated circuit. A switch may include a plurality of ports configured to receive a plurality of packets, and an integrated circuit configured to monitor a rate of the plurality of packets received at the switch. The integrated circuit may be configured to adjust a power consumption of at least part of the switch in response to the rate of the plurality of packets received at the switch.

摘要翻译： 根据一个实施例的方法可以包括通过交换机的集成电路接收多个分组，监视在集成电路处接收的多个分组的速率，以及调整集成的至少一部分的功率消耗 响应于在集成电路处接收的多个分组的速率的电路。 交换机可以包括被配置为接收多个分组的多个端口，以及被配置为监视在该交换机处接收到的多个分组的速率的集成电路。 集成电路可以被配置为响应于在交换机处接收的多个分组的速率来调整交换机的至少一部分的功耗。

公开(公告)号：US20090239491A1

公开(公告)日：2009-09-24

申请号：US12477339

申请日：2009-06-03

申请人： Keith BARGROFF ,  Dale HANCOCK

发明人： Keith BARGROFF ,  Dale HANCOCK

IPC分类号： H04B1/06

CPC分类号： H04B1/126 ,  H03D7/00 ,  H03D7/1425 ,  H03D7/1433 ,  H03D7/1458 ,  H03D2200/0025 ,  H03D2200/0043 ,  H03F3/19 ,  H03F2200/171 ,  H03F2200/294 ,  H03F2200/451 ,  H03G3/3036 ,  H04H40/90 ,  H04N7/102 ,  H04N7/20 ,  H04Q3/521 ,  H04Q2213/1302 ,  H04Q2213/13034 ,  H04Q2213/1304 ,  H04Q2213/1319 ,  H04Q2213/13322

摘要： A cascadable AGC amplifier in a signal distribution system includes a low noise cascadable amplifier having a through path and a cascadable output. The cascadable amplifier is also configured to provide AGC over a predetermined input power range. The cascadable AGC amplifier can be configured to provide gain or attenuation. When the cascadable AGC amplifier is implemented in a signal distribution system, typically as part of a signal distribution device, an input signal can be gain controlled and supplied to multiple signal paths without distortion due to degradation of signal to noise ratio or distortion due to higher order amplifier products. The distributed signal is not significantly degraded by distortion regardless of the number of cascadable AGC amplifiers connected in series or the position of the cascadable AGC amplifier in the signal distribution system.

摘要翻译： 信号分配系统中的级联AGC放大器包括具有通路和可级联输出的低噪声可级联放大器。 可级联放大器还被配置为在预定输入功率范围上提供AGC。 可级联AGC放大器可以配置为提供增益或衰减。 当级联AGC放大器在信号分配系统中实施时，通常作为信号分配装置的一部分，可以将输入信号增益控制并提供给多个信号路径，而不会由于信号噪声比的降低或由于较高 订单放大器产品。 无论串联连接的级联AGC放大器的数量或信号分配系统中的级联AGC放大器的位置如何，分布式信号都不会由于失真而显着降级。

公开(公告)号：US20050238052A1

公开(公告)日：2005-10-27

申请号：US11108971

申请日：2005-04-19

申请人： Takeshi Yamazaki

发明人： Takeshi Yamazaki

IPC分类号： G06F13/38 ,  G06F15/173 ,  H04L12/56 ,  H04L29/06 ,  H04L29/08 ,  H04Q3/52

CPC分类号： H04Q3/521 ,  G06F15/17393 ,  H04L49/101 ,  H04L49/25 ,  H04L49/358 ,  H04L69/08 ,  H04L69/18 ,  H04L69/32 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13076 ,  H04Q2213/13215 ,  H04Q2213/13292

摘要： Method and apparatus are provided for improved connection of devices and lower latency of communications between devices of a massively parallel network. In particular, method and apparatus are provided for cross-bar switches, a multiple protocol interface device, a low latency upper communication protocol layer, addressing and remote direct memory access over a massively parallel network.

摘要翻译： 提供了用于改进设备连接和较大并行网络的设备间通信延迟较低的方法和装置。 特别地，提供了用于跨条形交换机，多协议接口设备，低延迟上层通信协议层，通过大规模并行网络的寻址和远程直接存储器访问的方法和装置。

公开(公告)号：US06901070B2

公开(公告)日：2005-05-31

申请号：US09729531

申请日：2000-12-04

申请人： Gautam Nag Kavipurapu

发明人： Gautam Nag Kavipurapu

IPC分类号： H04L12/56 ,  H04Q3/52 ,  H04L12/50

CPC分类号： H04L49/405 ,  H04L49/201 ,  H04L49/3027 ,  H04L49/351 ,  H04L49/40 ,  H04Q3/521 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13103 ,  H04Q2213/13305 ,  H04Q2213/1332 ,  H04Q2213/13322

摘要： A switching element including first, second and third ports each comprising a plurality of lines is disclosed. A first memory cell includes a storage element, a first pass gate for selectively coupling a first line of the first port to the storage element, a second pass gate for selectively coupling a first line of the second port to the storage element, and a third pass gate for selectively coupling a first line of the third port to the storage element. A second memory cell includes a storage element, a first gate for selectively coupling a second line of the first port to the storage element, a second pass gate for selectively coupling a second line of the second port to the storage element, and a third pass gate for selectively coupling a second line of the third port to the storage element.

摘要翻译： 公开了一种包括第一，第二和第三端口的开关元件，每个端口包括多条线路。 第一存储单元包括存储元件，用于选择性地将第一端口的第一线耦合到存储元件的第一通孔，用于选择性地将第二端口的第一线耦合到存储元件的第二通孔，以及第三通孔 用于选择性地将第三端口的第一线耦合到存储元件。 第二存储单元包括存储元件，用于选择性地将第一端口的第二线耦合到存储元件的第一栅极，用于选择性地将第二端口的第二线耦合到存储元件的第二栅极，以及第三通道 用于选择性地将第三端口的第二线路耦合到存储元件。

公开(公告)号：US06807186B2

公开(公告)日：2004-10-19

申请号：US10052233

申请日：2002-01-17

申请人： William J. Dally ,  John Edmondson ,  Donald A. Priore ,  Ephrem Wu ,  John W. Poulton

发明人： William J. Dally ,  John Edmondson ,  Donald A. Priore ,  Ephrem Wu ,  John W. Poulton

IPC分类号： H04L1228

CPC分类号： H04L49/405 ,  H04Q3/521

摘要： A single-stage grooming switch is provided for switching streams of multiplexed traffic, such as SONET STS-48, in both time and space domains. In particular, the switch implements a distributed demultiplexing architecture for switching between any input timeslot to any output timeslot at a reduced layout size. Furthermore, the distributed demultiplexing architecture results in low latencies being associated with reconfiguration of output permutations on the order of nanoseconds.

摘要翻译： 提供单级梳理开关，用于在时域和空间域中切换多路复用业务流，如SONET STS-48。 特别地，交换机实现分布式解复用架构，用于在减少的布局大小的任何输入时隙之间切换到任何输出时隙。 此外，分布式解复用架构导致低延迟与纳秒级的输出排列的重新配置相关联。

公开(公告)号：US20040062228A1

公开(公告)日：2004-04-01

申请号：US10341546

申请日：2003-01-13

申请人： Velio Communications, Inc.

发明人： Ephrem C. Wu

IPC分类号： H04L012/28

CPC分类号： H04J3/1611 ,  H04Q3/521 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13076 ,  H04Q2213/13103 ,  H04Q2213/13322

摘要： Two or more cross-connect ICs are interconnected. Each IC directly receives some, but not all, of the system inputs, and outputs to some, but not all, outputs. Each cross-connect IC has a switch matrix that has the same number of inputs as the system, and a lesser number of outputs that matches the number of outputs of the IC. Each cross-connect IC provides fanout of its direct inputs to a link to each other cross-connect IC. Thus, each IC receives inputs either directly, or from a fanout on another IC.

摘要翻译： 两个或更多个交叉连接IC互连。 每个IC直接接收一些但不是全部的系统输入，并输出到一些但不是全部的输出。 每个交叉连接IC具有与系统相同数量的输入的开关矩阵，以及与IC的输出数量匹配的较少数量的输出。 每个交叉连接IC提供其直接输入的扇出到彼此交叉连接IC的链路。 因此，每个IC直接或从另一个IC上的扇出接收输入。

公开(公告)号：US20030030509A1

公开(公告)日：2003-02-13

申请号：US10198494

申请日：2002-07-18

发明人： Hugo Veenstra ,  Edwin Van Der Heijden ,  Mihai Adrian Tiberiu Sanduleanu

IPC分类号： H01P001/10

CPC分类号： H04Q3/521 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13305 ,  H04Q2213/13306

摘要： A transmission lines arrangement comprising a first plurality of transmission lines each transmission line having an effective characteristic impedance. The arrangement further comprises a second plurality of transmission lines, said first plurality of transmission lines being coupled to a plurality of switching elements. The plurality of switching elements are conceived to redirect an input signal from one transmission line of the first plurality of transmission lines to at least one transmission line of the second plurality of transmission lines. The arrangement is characterized in that each of the switching elements of the plurality of switching elements have a relatively high input impedance in comparison with the effective characteristic impedance and a relatively high output impedance in comparison with the effective characteristic impedance. Furthermore, each transmission line of the first plurality of transmission lines is further coupled to an impedance that is substantially equal to the effective characteristic impedance of said transmission line.

摘要翻译： 一种传输线布置，包括第一多个传输线，每个传输线具有有效的特征阻抗。 该布置还包括第二多个传输线，所述第一多个传输线耦合到多个开关元件。 多个开关元件被设想为将来自第一多个传输线的一个传输线的输入信号重定向到第二多个传输线的至少一个传输线。 该装置的特征在于，与有效特性阻抗相比，多个开关元件的每个开关元件与有效特性阻抗相比具有相对较高的输入阻抗和相对较高的输出阻抗。 此外，第一多个传输线的每个传输线还进一步耦合到基本上等于所述传输线的有效特性阻抗的阻抗。

公开(公告)号：US20020181482A1

公开(公告)日：2002-12-05

申请号：US10052233

申请日：2002-01-17

申请人： Velio Communications, Inc.

发明人： William J. Dally ,  John Edmondson ,  Donald A. Priore ,  Ephrem Wu ,  John W. Poulton

IPC分类号： H04L012/28

CPC分类号： H04L49/405 ,  H04Q3/521

摘要： A single-stage grooming switch is provided for switching streams of multiplexed traffic, such as SONET STS-48, in both time and space domains. In particular, the switch implements a distributed demultiplexing architecture for switching between any input timeslot to any output timeslot at a reduced layout size. Furthermore, the distributed demultiplexing architecture results in low latencies being associated with reconfiguration of output permutations on the order of nanoseconds.

摘要翻译： 提供单级梳理开关，用于在时域和空间域中切换多路复用业务流，如SONET STS-48。 特别地，交换机实现分布式解复用架构，用于在减少的布局尺寸下在任何输入时隙之间切换到任何输出时隙。 此外，分布式解复用架构导致低延迟与纳秒级的输出排列的重新配置相关联。

公开(公告)号：USRE34444E

公开(公告)日：1993-11-16

申请号：US725353

申请日：1991-07-03

申请人： Cecil H. Kaplinsky

发明人： Cecil H. Kaplinsky

IPC分类号： H03K19/177 ,  H04Q3/52 ,  H04Q1/00

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17792 ,  H04Q3/521

摘要： A programmable logic device architecture having a matrix of smaller functional units, each of which being a programmable logic array, and a set of fixed conductive lines connected to the functional unit inputs and outputs, the conductive lines forming programmable interconnection matrices. The input pins can be programmably connected to any input of any functional unit, and the outputs of functional units can be programmably connected to any input of any functional unit or any output pin. The interconnection matrices may be a simple array of crossing conductive lines with crossings connected by fuses, EPROM, or EEPROM switches or may have additional series switches to limit the effective impedance so as to speed propagation through these matrices. A fast path through one functional unit bypassing the interconnection matrices is available for a limited number of input and output pins. Multiplexers and other structures may be provided at ends of the fixed conductive lines to enable exhaustive testing of individual functional units, interconnections and logic, and structure may also be provided for on-chip monitoring of state information and providing the information to the external world when certain preselected events happen.

公开(公告)号：US5221922A

公开(公告)日：1993-06-22

申请号：US640530

申请日：1991-01-11

申请人： Gerhard Trumpp ,  Jan Wolkenhauer

发明人： Gerhard Trumpp ,  Jan Wolkenhauer

IPC分类号： H03K17/693 ,  H04Q3/52

CPC分类号： H04Q3/521 ,  H03K17/693

摘要： In a broadband signal switching matrix network having a cross-point matrix in FET technology whose switching elements, controlled by a holding memory cell, are each formed with a series circuit of a switching transistor and of an input transistor. Matrix output lines thereof are respectively connected to one terminal of the operating voltage source via a pre-charging transistor that is controlled by a pre-charging clock, that side of the series circuit connected opposite from the matrix output line being permanently connected to the other terminal of the operating voltage source (directly or via a transistor controlled by the output signal and individually associated to the matrix output line) in order to avoid sample clock lines that lead to the switching elements.

摘要翻译： 在具有FET技术中的交叉点矩阵的宽带信号交换矩阵网络中，由保持存储单元控制的开关元件各自由开关晶体管和输入晶体管的串联电路形成。 其矩阵输出线分别经由由预充电时钟控制的预充电晶体管连接到工作电压源的一个端子，与矩阵输出线相对连接的串联电路的一侧永久连接到另一端 端子（直接或通过由输出信号控制并且单独地与矩阵输出线相关联的晶体管），以避免导致开关元件的采样时钟线。