Abstract:
The present application discloses apparatus and methods for increasing channel utilization for a high-speed serial interface of an integrated circuit (IC). A new circuit architecture is disclosed which provides circuitry that may be programmed flexibly to support a multitude of different channel bonding schemes. In accordance with one aspect of the invention, the new architecture decouples the granularity of control-signal channel bonding from the granularity of data-aggregation channel bonding. This advantageously allows optimization of configurations for both types of channel bonding. In another aspect of the invention, the logical boundaries of bonded user channels are decoupled from the physical boundaries of the PCS modules. This decoupling advantageously eliminates a rigid constraint of previous architectures.
Abstract:
A telemetry system is described in which a plurality of channels are coupled to a bus. A control subsystem controls the channels so that one of the channels presents to the bus during its designated time period a channel characteristic. The control subsystem interrogates in the analog domain each of the channels during its designated time period, and forms a signal representative of the channel characteristic. The control subsystem may combine one or more of the signals into a digital packet, and transmit the same via transceiver over a wireless network. The channels may be contained within a submersible enclosure and displaced at intervals along the bus, thereby forming an array for monitoring waterborne threats. The array may lie along an ocean floor, may be towed by a marine vehicle, or may suspended from a deployable buoy containing the control subsystem, transceiver, and a remote power source. The array may further comprise a defensive countermeasure deployable responsive to detecting a threat.
Abstract:
A connection device for random connection of a first member of first transmission/reception units with a second number of second transmission/reception units has a switching matrix that includes a third number of controllable micromechanical switching elements that are respectively activatable to establish a connection between one of the first transmission/reception units and one of the second transmission/reception units. A control circuit selectively activates the respective micromechanical switching elements to selectively establish respective connections between the first number of first transmission/reception units and the second number of transmission/reception units.
Abstract:
An Internet Protocol (IP) multimedia subsystem for use in a telecommunication network. The IP multimedia subsystem comprises: 1) an IP switch for receiving Common Open Policy Service (COPS) protocol messages from an external IP network; and 2) a plurality of call application nodes capable of executing a plurality of Policy Decision Function (PDF) application groups. The IP switch distributes the COPS messages to the plurality of call application nodes according to a load-sharing algorithm.
Abstract:
Embodiments of a bidirectional 3-way optical splitter are described. This bidirectional 3-way optical splitter includes an optical splitter having: a first external node, a second external node, a third external node, and a fourth external node. In one mode of operation, the optical splitter may be configured to receive an external input optical signal on the first external node and to provide external output optical signals on the other external nodes. Moreover, in another mode of operation, the optical splitter may be configured to receive the external input optical signal on the third external node and to provide the external output optical signals on the other external nodes.
Abstract:
A method of filtering streaming digital data in real time. The method including: (a) initializing and storing a set of m data elements and an associated set of m pointer data from 1 to m in sequence, m an integer greater than 2; (b) receiving in real time a first or next data element of a digital data stream of sequential data elements; (c) simultaneously with (b), replacing a stored data element associated with the pointer datum m with the received data element, changing the pointer datum of m to 1, and incrementing the value of all other pointer data by 1; (d) simultaneously with (b) sorting in order from a low to high all stored data elements; (e) simultaneously with (b), maintaining the association of pointer datum and data elements; (f) simultaneously with (b), filtering all stored data elements; and (g) repeating (b) through (f) multiple times.
Abstract:
An apparatus and method for effecting sophisticated telephony services using hybrid POTS and VoIP transport without resorting to central servers or PBXs is provided. Key to the system is the use of on-phone processing capabilities comprising several A-D/D-A, memory and addressing, audio-mixing, program memory and programmable computing circuits or components. The system performs required IP and VoIP protocol stacks (UDP, RTP, and SIP for example) and POTS functionality. Optionally, fail-over from set-power may be provided using POTS line voltages.The phones of this invention self-configure dependent upon the network environment to which they are attached, and direct call and other functionality digitally under programmed computing control, thus being highly configurable; redundancy between networked phone devices adds robustness.The telephone system is comprised of independent telephony devices operating on a LAN and/or WAN TCP/IP-based connection The inventive concept allows for greater system scalability with lower cost, reliability and flexibility.
Abstract:
A system for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the computing cluster are synchronized. Internal system clock signals are generated in each of the processor chips based on the synchronized heartbeat signals. As a result, the internal system clock signals of each of the processor chips are synchronized since the heartbeat signals, that are the basis for the internal system clock signals, are synchronized. Mechanisms are provided for performing such synchronization using direct couplings of processor chips within the same processor book, different processor books in the same supernode, and different processor books in different supernodes of the MTFG interconnect architecture.
Abstract:
A multi-port link interface capable of high-speed time division multiplexed communications at a signal transfer point is disclosed. In one implementation, the multi-port link interface module is located in the signal transfer point, terminates two or more high-speed TDM links and generates internal data. Data received on one high-speed communications link is combined with the internal data used to fill outbound timeslots in an outgoing high-speed link. The data may include signaling data, bearer data, or signaling and bearer data.
Abstract:
A system and method for protection switching in a transmission network is described. A protection switching mechanism comprises a multiplexer, a transmission path for each output of the multiplexer and a remote circuit. The multiplexer has an input coupled to receive an input signal and a plurality of outputs to output a plurality of output signals. Each transmission path is coupled to receive an associated output signal from the multiplexer. The transmission paths further include one or more redundant transmission paths, wherein signals directed to a faulty transmission path are redirected to an associated redundant transmission path. The remote circuit is used to selectively switch a redundant transmission path for a faulty transmission path at a subscriber.