公开(公告)号：US07219264B2

公开(公告)日：2007-05-15

申请号：US10435077

申请日：2003-05-09

Applicant: Michael R. Pail ,  Robert Wallace ,  Jeremy T. Baus

Inventor： Michael R. Pail ,  Robert Wallace ,  Jeremy T. Baus

IPC: G06F11/00

CPC classification number: G06F11/0793 ,  G06F11/073 ,  G06F11/0757

Abstract: Methods and systems for preserving dynamic random access memory content in response to a hung processor condition are disclosed. In order to preserve dynamic random access memory content, a first watchdog timer is initiated and strobed at a predetermined time interval less than its timeout value. If a hung processor condition occurs and the strobing of the first watchdog timer fails, the first watchdog timer generates a non-maskable interrupt to the processor. The non-maskable interrupt triggers the processor to execute an interrupt service routine. If the processor is able to execute the interrupt service routine, the interrupt service routine controls the processor to perform a selective system reset and preserve dynamic random access memory contents. If the processor is not capable of executing the interrupt service routine, a board reset occurs and dynamic random access memory contents are cleared.

Abstract translation: 公开了用于响应于挂起处理器条件来保留动态随机存取存储器内容的方法和系统。 为了保留动态随机存取存储器内容，第一看门狗定时器以小于其超时值的预定时间间隔发起并选通。 如果出现挂起的处理器状况，并且第一个看门狗定时器的选通程序失败，则第一个看门狗定时器向处理器产生不可屏蔽的中断。 不可屏蔽中断触发处理器执行中断服务程序。 如果处理器能够执行中断服务程序，则中断服务程序控制处理器执行选择性系统复位并保留动态随机存取存储器内容。 如果处理器不能执行中断服务程序，则会发生电路板复位，并清除动态随机存取存储器内容。

公开(公告)号：US07075331B2

公开(公告)日：2006-07-11

申请号：US10860189

申请日：2004-06-03

Applicant: Michael R. Pail ,  Jeremy T. Baus ,  Robert Wallace

Inventor： Michael R. Pail ,  Jeremy T. Baus ,  Robert Wallace

IPC: G06F7/38 ,  H03K19/173 ,  H03K19/177

CPC classification number: G06F17/5054

Abstract: A programmable logic device (PLD) in a microprocessor system is programmed with minimal load on system resources. A microprocessor reads programming data from a first memory using a parallel bussed interface and writes the programming data to a programming hardware assist engine using the parallel bussed interface. The programming hardware assist engine directs a portion of the programming data to a specified serial interface signal, and outputs a serial bit stream from the programming hardware assist engine to a serial programming interface of the PLD using the specified serial interface signal.

Abstract translation: 微处理器系统中的可编程逻辑器件（PLD）以系统资源的最小负载进行编程。 微处理器使用并行总线接口从第一存储器读取编程数据，并使用并行总线接口将编程数据写入编程硬件辅助引擎。 编程硬件辅助引擎将编程数据的一部分引导到指定的串行接口信号，并使用指定的串行接口信号将串行比特流从编程硬件辅助引擎输出到PLD的串行编程接口。

公开(公告)号：US07468988B2

公开(公告)日：2008-12-23

申请号：US10225998

申请日：2002-08-22

Applicant: Michael R. Pail ,  Phillip C. Jerzak, Jr. ,  John R. Lenns ,  Todd Eichler ,  Neil Tomlinson ,  Peter J. Marsico

Inventor： Michael R. Pail ,  Phillip C. Jerzak, Jr. ,  John R. Lenns ,  Todd Eichler ,  Neil Tomlinson ,  Peter J. Marsico

IPC: H04J3/16

CPC classification number: H04Q3/0025 ,  H04Q11/0414 ,  H04Q11/0421 ,  H04Q2213/13003 ,  H04Q2213/13097 ,  H04Q2213/13103 ,  H04Q2213/13106 ,  H04Q2213/13176 ,  H04Q2213/13214 ,  H04Q2213/13216 ,  H04Q2213/13292 ,  H04Q2213/13299 ,  H04Q2213/1332 ,  H04Q2213/13322 ,  H04Q2213/13362 ,  H04Q2213/13392

Abstract: A multi-port link interface capable of high-speed time division multiplexed communications at a signal transfer point is disclosed. In one implementation, the multi-port link interface module is located in the signal transfer point, terminates two or more high-speed TDM links and generates internal data. Data received on one high-speed communications link is combined with the internal data used to fill outbound timeslots in an outgoing high-speed link. The data may include signaling data, bearer data, or signaling and bearer data.

Abstract translation: 公开了一种能够在信号传送点进行高速时分复用通信的多端口链路接口。 在一个实现中，多端口链路接口模块位于信号传输点，终止两个或多个高速TDM链路，并产生内部数据。 在一个高速通信链路上接收的数据与用于在外发高速链路中填写出站时隙的内部数据组合。 数据可以包括信令数据，承载数据或信令和承载数据。