公开(公告)号：US08302109B2

公开(公告)日：2012-10-30

申请号：US12391373

申请日：2009-02-24

申请人： Lakshminarayana Arimilli ,  Claude Basso ,  Piyush Chaudhary ,  Bernard C. Drerup ,  Jody B. Joyner ,  Jan-Bernd Themann ,  Christoph Raisch ,  Colin B. Verrilli

发明人： Lakshminarayana Arimilli ,  Claude Basso ,  Piyush Chaudhary ,  Bernard C. Drerup ,  Jody B. Joyner ,  Jan-Bernd Themann ,  Christoph Raisch ,  Colin B. Verrilli

IPC分类号： G06F3/03

CPC分类号： G06F9/545 ,  G06F9/546

摘要： A synchronization optimized queuing method and device to minimize software/hardware interaction in network interface hardware during an end-of-initiative process, including network adapter queue implementations for network interface hardware for optimized communication in a computer system. An end-of-initiative procedure to ensure that the network interface hardware has received an interrupt enable and to recheck the interrupt queue is unnecessary in the present invention.

摘要翻译： 一种同步优化的排队方法和设备，用于最大程度地减少网络接口硬件中的软件/硬件交互，包括用于计算机系统中优化通信的网络接口硬件的网络适配器队列实现。 在本发明中，确保网络接口硬件已经接收到中断使能并重新检查中断队列的最终主动性过程是不必要的。

公开(公告)号：US07827428B2

公开(公告)日：2010-11-02

申请号：US11848440

申请日：2007-08-31

申请人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Bernard C. Drerup ,  Jody B. Joyner ,  Jerry D. Lewis

发明人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Bernard C. Drerup ,  Jody B. Joyner ,  Jerry D. Lewis

IPC分类号： G06F1/00 ,  G06F1/04 ,  G06F1/12

CPC分类号： G06F1/12 ,  H04J3/0685 ,  H04Q2213/13092 ,  H04Q2213/13214 ,  H04Q2213/13322 ,  H04Q2213/1336

摘要： A system for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the computing cluster are synchronized. Internal system clock signals are generated in each of the processor chips based on the synchronized heartbeat signals. As a result, the internal system clock signals of each of the processor chips are synchronized since the heartbeat signals, that are the basis for the internal system clock signals, are synchronized. Mechanisms are provided for performing such synchronization using direct couplings of processor chips within the same processor book, different processor books in the same supernode, and different processor books in different supernodes of the MTFG interconnect architecture.

摘要翻译： 提供了一种用于在多层全图（MTFG）互连架构中提供集群范围的系统时钟的系统。 计算群集中的每个处理器芯片发送的心跳信号同步。 基于同步的心跳信号，在每个处理器芯片中产生内部系统时钟信号。 结果，每个处理器芯片的内部系统时钟信号被同步，因为作为内部系统时钟信号的基础的心跳信号被同步。 提供了用于使用同一处理器书中的处理器芯片的直接耦合，同一超级节点中的不同处理器书以及MTFG互连体系结构的不同超节点中的不同处理器簿来执行这种同步的机制。

公开(公告)号：US07685373B2

公开(公告)日：2010-03-23

申请号：US11970599

申请日：2008-01-08

申请人： James N. Dieffenderfer ,  Bernard C. Drerup ,  Jaya P. Ganasan ,  Richard G. Hofmann ,  Thomas A. Sartorius ,  Thomas P. Speier ,  Barry J. Wolford

发明人： James N. Dieffenderfer ,  Bernard C. Drerup ,  Jaya P. Ganasan ,  Richard G. Hofmann ,  Thomas A. Sartorius ,  Thomas P. Speier ,  Barry J. Wolford

IPC分类号： G06F12/00

CPC分类号： G06F12/0831 ,  Y02D10/13

摘要： A system and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has a cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originating snooping master and wherein the needed data in an non-originating snooping master is marked as updated, and wherein a main memory having addresses for all data is connected to the bus macro. Only those non-originating snooping masters which may have the requested data are queried. All the non-originating snooping masters that have been queried reply. If a non-originating snooping master has the requested data marked as updated, that non-originating snooping master returns the updated data to the originating snooping master and possibly to the main memory. If none of the non-originating snooping masters has the requested data marked as updated, then the requested data is read from main memory.

摘要翻译： 一种用于窥探连接到总线宏的多个窥探主机的高速缓存存储器的系统和结构，其中每个非起始侦听主机具有高速缓冲存储器，并且其中一些但不到全部高速缓冲存储器可具有始发请求的数据 窥探主机，其中在非始发侦听主机中所需的数据被标记为更新，并且其中具有用于所有数据的地址的主存储器连接到总线宏。 只有那些可能具有请求的数据的非始发侦听主机才被查询。 所有被查询的非始发侦听主人都回复。 如果非始发侦听主机具有被标记为更新的请求数据，则该非起始侦听主机会将更新的数据返回给始发侦听主机，并将其返回到主内存。 如果非始发侦听主机中没有一个被标记为已更新的请求数据，则从主存储器读取所请求的数据。

公开(公告)号：US07668996B2

公开(公告)日：2010-02-23

申请号：US11877296

申请日：2007-10-23

申请人： Bernard C. Drerup ,  Richard Nicholas

发明人： Bernard C. Drerup ,  Richard Nicholas

IPC分类号： G06F13/36 ,  G06F13/00 ,  H04L12/28

CPC分类号： G06F13/364

摘要： An improved method, device and data processing system are presented. In one embodiment, the method includes a source device sending a request for a bus grant to deliver data to a data bus connecting a source device and a destination device. The device receives the bus grant and logic within the device determines whether the bandwidth of the data bus allocated to the bus grant will be filled by the data. If the bandwidth of the data bus allocated to the bus grant will not be filled by the data, the device appends additional data to the first data and delivers the combined data to the data bus during the bus grant for the first data. When the bandwidth of the data bus allocated to the bus grant will be filled by the first data, the device delivers only the first data to the data bus during the bus grant.

摘要翻译： 提出了一种改进的方法，设备和数据处理系统。 在一个实施例中，该方法包括发送对总线许可的请求的源设备，以向连接源设备和目的地设备的数据总线传送数据。 设备接收总线许可，并且设备内的逻辑确定分配给总线授权的数据总线的带宽是否将被数据填充。 如果分配给总线授权的数据总线的带宽不会被数据填充，则设备将附加数据附加到第一个数据，并在第一个数据的总线授权期间将组合的数据传送到数据总线。 当分配给总线授权的数据总线的带宽将由第一个数据填充时，设备在总线授权期间只将第一个数据传送到数据总线。

公开(公告)号：US20090070617A1

公开(公告)日：2009-03-12

申请号：US11853522

申请日：2007-09-11

申请人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Bernard C. Drerup ,  Jody B. Joyner ,  Jerry D. Lewis

发明人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Bernard C. Drerup ,  Jody B. Joyner ,  Jerry D. Lewis

IPC分类号： G06F1/12

CPC分类号： G06F1/10 ,  G06F1/12

摘要： A method for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the computing cluster are synchronized. Internal system clock signals are generated in each of the processor chips based on the synchronized heartbeat signals. As a result, the internal system clock signals of each of the processor chips are synchronized since the heartbeat signals, that are the basis for the internal system clock signals, are synchronized. Mechanisms are provided for performing such synchronization using direct couplings of processor chips within the same processor book, different processor books in the same supernode, and different processor books in different supernodes of the MTFG interconnect architecture.

摘要翻译： 提供了一种在多层全图（MTFG）互连架构中提供集群范围的系统时钟的方法。 计算群集中的每个处理器芯片发送的心跳信号同步。 基于同步的心跳信号，在每个处理器芯片中产生内部系统时钟信号。 结果，每个处理器芯片的内部系统时钟信号被同步，因为作为内部系统时钟信号的基础的心跳信号被同步。 提供了用于使用同一处理器书中的处理器芯片的直接耦合，同一超级节点中的不同处理器书以及MTFG互连体系结构的不同超节点中的不同处理器簿来执行这种同步的机制。

公开(公告)号：US08751655B2

公开(公告)日：2014-06-10

申请号：US12749100

申请日：2010-03-29

申请人： Lakshminarayana B. Arimilli ,  Bernard C. Drerup ,  Paul F. Lecocq ,  Hanhong Xue

发明人： Lakshminarayana B. Arimilli ,  Bernard C. Drerup ,  Paul F. Lecocq ,  Hanhong Xue

IPC分类号： G06F15/173

CPC分类号： H04L29/06 ,  G06F15/17318 ,  H04L12/56 ,  H04L29/08072 ,  H04L29/08135 ,  H04L29/12132 ,  H04L29/12594 ,  H04L45/02 ,  H04L45/123 ,  H04L45/306 ,  H04L61/1552 ,  H04L61/3015 ,  Y10S707/9994

摘要： A mechanism is provided in a collective acceleration unit for performing a collective operation to distribute or collect data among a plurality of participant nodes. The mechanism receives an input collective packet for a collective operation from a neighbor node within a collective tree. The input collective packet comprises a tree identifier and an input data field and wherein the collective tree comprises a plurality of sub trees. The mechanism maps the tree identifier to an index within the collective acceleration unit. The index identifies a portion of resources within the collective acceleration unit and is associated with a set of neighbor nodes in a given sub tree within the collective tree. For each neighbor node the collective acceleration unit stores destination information. The collective acceleration unit performs an operation on the input data field using the portion of resources to effect the collective operation.

摘要翻译： 在集体加速单元中提供一种用于执行集合操作以在多个参与者节点之间分发或收集数据的机制。 该机制从集体树中的邻居节点接收用于集体操作的输入集合分组。 所述输入集合分组包括树标识符和输入数据字段，并且其中所述集合树包括多个子树。 该机制将树标识符映射到集体加速单元内的索引。 索引识别集体加速单元内的资源的一部分，并且与集合树内的给定子树中的一组相邻节点相关联。 对于每个邻居节点，集体加速单元存储目的地信息。 集体加速单元使用资源部分对输入数据字段进行操作以实现集体操作。

公开(公告)号：US20120296915A1

公开(公告)日：2012-11-22

申请号：US13454727

申请日：2012-04-24

申请人： Lakshminarayana B. Arimilli ,  Bernard C. Drerup ,  Paul F. Lecocq ,  Hanhong Xue

发明人： Lakshminarayana B. Arimilli ,  Bernard C. Drerup ,  Paul F. Lecocq ,  Hanhong Xue

IPC分类号： G06F17/30

CPC分类号： H04L29/06 ,  G06F15/17318 ,  H04L12/56 ,  H04L29/08072 ,  H04L29/08135 ,  H04L29/12132 ,  H04L29/12594 ,  H04L45/02 ,  H04L45/123 ,  H04L45/306 ,  H04L61/1552 ,  H04L61/3015 ,  Y10S707/9994

摘要： A mechanism is provided in a collective acceleration unit for performing a collective operation to distribute or collect data among a plurality of participant nodes. The mechanism receives an input collective packet for a collective operation from a neighbor node within a collective tree. The input collective packet comprises a tree identifier and an input data field and wherein the collective tree comprises a plurality of sub trees. The mechanism maps the tree identifier to an index within the collective acceleration unit. The index identifies a portion of resources within the collective acceleration unit and is associated with a set of neighbor nodes in a given sub tree within the collective tree. For each neighbor node the collective acceleration unit stores destination information. The collective acceleration unit performs an operation on the input data field using the portion of resources to effect the collective operation.

摘要翻译： 在集体加速单元中提供一种用于执行集合操作以在多个参与者节点之间分发或收集数据的机制。 该机制从集体树中的邻居节点接收用于集体操作的输入集合分组。 所述输入集合分组包括树标识符和输入数据字段，并且其中所述集合树包括多个子树。 该机制将树标识符映射到集体加速单元内的索引。 索引识别集体加速单元内的资源的一部分，并且与集合树内的给定子树中的一组相邻节点相关联。 对于每个邻居节点，集体加速单元存储目的地信息。 集体加速单元使用资源部分对输入数据字段进行操作以实现集体操作。

公开(公告)号：US08077602B2

公开(公告)日：2011-12-13

申请号：US12024514

申请日：2008-02-01

申请人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Bernard C. Drerup ,  Jody B. Joyner ,  Jerry D. Lewis

发明人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Bernard C. Drerup ,  Jody B. Joyner ,  Jerry D. Lewis

IPC分类号： G01R31/08 ,  G06F11/00 ,  G08C15/00 ,  H04J1/16 ,  H04J3/14 ,  H04L1/00 ,  H04L12/26 ,  H04L12/28 ,  H04L12/56

CPC分类号： G06F15/17

摘要： Mechanisms for performing dynamic request routing based on broadcast depth queue information are provided. Each processor chip in the system may use a synchronized heartbeat signal it generates to provide queue depth information to each of the other processor chips in the system. The queue depth information identifies a number of requests or amount of data in each of the queues of a processor chip that originated the heartbeat signal. The queue depth information from each of the processor chips in the system may be used by the processor chips in determining optimal routing paths for data from a source processor chip to a destination processor chip. As a result, the congestion of data for processing at each of the processor chips along each possible routing path may be taken into account when selecting to which processor chip to forward data.

摘要翻译： 提供了基于广播深度队列信息执行动态请求路由的机制。 系统中的每个处理器芯片可以使用其产生的同步心跳信号来向系统中的每个其他处理器芯片提供队列深度信息。 队列深度信息识别发起心跳信号的处理器芯片的每个队列中的数量的请求或数据量。 系统中每个处理器芯片的队列深度信息可被处理器芯片用于确定用于从源处理器芯片到目的地处理器芯片的数据的最佳路由路径。 结果，当选择哪个处理器芯片来转发数据时，可以考虑在每个可能的路由路径处的每个处理器芯片处理数据的拥塞。

公开(公告)号：US20110173258A1

公开(公告)日：2011-07-14

申请号：US12640208

申请日：2009-12-17

申请人： Lakshminarayana B. Arimilli ,  Bernard C. Drerup ,  Jody B. Joyner ,  Paul F. Lecocq ,  Hanhong Xue

发明人： Lakshminarayana B. Arimilli ,  Bernard C. Drerup ,  Jody B. Joyner ,  Paul F. Lecocq ,  Hanhong Xue

IPC分类号： G06F15/16

CPC分类号： G06F15/16

摘要： A mechanism is provided for collective acceleration unit tree flow control forms a logical tree (sub-network) among those processors and transfers “collective” packets on this tree. The system supports many collective trees, and each collective acceleration unit (CAU) includes resources to support a subset of the trees. Each CAU has limited buffer space, and the connection between two CAUs is not completely reliable. Therefore, to address the challenge of collective packets traversing on the tree without colliding with each other for buffer space and guaranteeing the end-to-end packet delivery, each CAU in the system effectively flow controls the packets, detects packet loss, and retransmits lost packets.

摘要翻译： 提供了一种用于集体加速单元树流控制的机制，形成这些处理器之间的逻辑树（子网），并在该树上传输“集合”分组。 系统支持许多集体树，每个集体加速单元（CAU）包括支持一部分树的资源。 每个CAU具有有限的缓冲区空间，两个CAU之间的连接不是完全可靠的。 因此，为了解决在树上遍历的集合分组的挑战，不会相互冲突，保证端到端的分组传递，系统中的每个CAU都有效地流量控制分组，检测分组丢失，重传丢失 数据包

公开(公告)号：US07779148B2

公开(公告)日：2010-08-17

申请号：US12024553

申请日：2008-02-01

申请人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Bernard C. Drerup ,  Jody B. Joyner ,  Jerry D. Lewis

发明人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Bernard C. Drerup ,  Jody B. Joyner ,  Jerry D. Lewis

IPC分类号： G06F15/163

CPC分类号： H04L45/122 ,  H04L45/06

摘要： A mechanism for performing dynamic request routing based on broadcast source request information is provided. Each processor chip in the system may use a synchronized heartbeat signal it generates to provide source request information to each of the other processor chips in the system. The source request information identifies the number of active source requests sent by the processor chip that originated the heartbeat signal. The source request information from each of the processor chips in the system may be used by the processor chips in determining optimal routing paths for data from a source processor chip to a destination processor chip. As a result, the congestion of data for processing at each of the processor chips along each possible routing path may be taken into account when selecting to which processor chip to forward data.

摘要翻译： 提供了一种基于广播源请求信息进行动态请求路由的机制。 系统中的每个处理器芯片可以使用其产生的同步心跳信号来向系统中的每个其他处理器芯片提供源请求信息。 源请求信息标识由发起心跳信号的处理器芯片发送的活动源请求的数量。 来自系统中的每个处理器芯片的源请求信息可被处理器芯片用于确定用于从源处理器芯片到目的地处理器芯片的数据的最佳路由路径。 结果，当选择哪个处理器芯片来转发数据时，可以考虑在每个可能的路由路径处的每个处理器芯片处理数据的拥塞。