公开(公告)号：US20160294452A1

公开(公告)日：2016-10-06

申请号：US15187409

申请日：2016-06-20

Applicant: IPR LICENSING, INC.

Inventor： Gary L. Sugar ,  Robert M. Masucci ,  David G. Rahn

IPC: H04B7/04 ,  H04B1/403 ,  H04B1/00

CPC classification number: H04B7/0413 ,  H03D2200/0025 ,  H04B1/005 ,  H04B1/0057 ,  H04B1/006 ,  H04B1/406

Abstract: As disclosed herein is a multiple-input multiple-output (MIMO) radio transceiver which may include a plurality of antennas operatively coupled to a first integrated circuit (IC). The first IC and the plurality of antennas may receive a first radio signal on a first radio frequency (RF) carrier and a second radio signal on a second RF carrier. The first RF carrier and the second RF carrier may be different carriers. The first radio signal and the second radio signal may have different bandwidths. The first IC may demodulate the first received radio signal to produce a first baseband signal and the second received radio signal to produce a second baseband signal. A second IC may be operatively coupled to the first IC and may recover data from at least the first baseband signal and the second baseband signal.

Abstract translation: 如本文所公开的是可以包括可操作地耦合到第一集成电路（IC）的多个天线的多输入多输出（MIMO）无线电收发器。 第一IC和多个天线可以在第一射频（RF）载波上接收第一无线电信号，并在第二RF载波上接收第二无线电信号。 第一RF载波和第二RF载波可以是不同的载波。 第一无线电信号和第二无线电信号可以具有不同的带宽。 第一IC可以解调第一接收的无线电信号以产生第一基带信号和第二接收的无线电信号以产生第二基带信号。 第二IC可以可操作地耦合到第一IC，并且可以从至少第一基带信号和第二基带信号恢复数据。

公开(公告)号：US08929840B2

公开(公告)日：2015-01-06

申请号：US12209164

申请日：2008-09-11

Applicant: Sankaran Aniruddhan ,  Chiewcharn Narathong ,  Sriramgopal Sridhara ,  Ravi Sridhara ,  Gurkanwal Singh Sahota ,  Frederic Bossu ,  Ojas M. Choksi

Inventor： Sankaran Aniruddhan ,  Chiewcharn Narathong ,  Sriramgopal Sridhara ,  Ravi Sridhara ,  Gurkanwal Singh Sahota ,  Frederic Bossu ,  Ojas M. Choksi

IPC: H04B1/02 ,  H04B1/06 ,  H04B7/00 ,  H04B1/26 ,  H03D7/16 ,  H03D7/14 ,  H03G3/30

CPC classification number: H03D7/166 ,  H03D7/1441 ,  H03D7/1483 ,  H03D7/165 ,  H03D2200/0025 ,  H03G3/3052

Abstract: Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an exemplary embodiment, LO buffer and/or mixer size may be increased when a receiver or transmitter operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver or transmitter operates in a low gain mode. In an exemplary embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific exemplary embodiments of LO buffers and mixers having adjustable size are disclosed.

Abstract translation: 公开了本地振荡器（LO）缓冲器和混频器的可选尺寸。 在示例性实施例中，当接收机或发射机以高增益模式工作时，可以增加LO缓冲器和/或混频器大小，而当接收机或发射机以低增益模式工作时，LO缓冲器和/或混频器大小可能会减小。 在示例性实施例中，锁定步骤中LO缓冲器和混合器尺寸增加和减小。 公开了具有可调节尺寸的LO缓冲器和混合器的具体示例性实施例的电路拓扑和控制方案。

公开(公告)号：US08774750B2

公开(公告)日：2014-07-08

申请号：US13930254

申请日：2013-06-28

Applicant: Silicon Laboratories Inc.

Inventor： Aslamali A. Rafi ,  Alessandro Piovaccari

IPC: H04B1/26

CPC classification number: H04B1/16 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1483 ,  H03D2200/0025 ,  H03D2200/0084 ,  H03D2200/0086 ,  H04N5/455

Abstract: In one embodiment, the present invention includes a method for receiving a radio frequency (RF) signal and mixing the RF signal with a master clock to obtain a mixed signal, cyclically rotating the mixed signal to each of N gain stages for at least one cycle of the master clock, and summing the outputs of the N gain stages to provide an output signal.

公开(公告)号：US08498598B2

公开(公告)日：2013-07-30

申请号：US13085601

申请日：2011-04-13

Applicant: Umut Basaran

Inventor： Umut Basaran

IPC: H04B17/00

CPC classification number: H03F3/45188 ,  H03D7/1433 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03D2200/0025 ,  H03D2200/0033 ,  H03D2200/0047 ,  H03F3/193 ,  H03F3/45659 ,  H03F2203/45048 ,  H03F2203/45244 ,  H03F2203/45371 ,  H03F2203/45396 ,  H03F2203/45481 ,  H03F2203/45616 ,  H03F2203/45631 ,  H04L27/364

Abstract: An RF-demodulator includes an RF-input, a demodulator output, a mixing and amplification stage coupled between the RF-input and the demodulator output, and a calibration circuitry. The calibration circuitry is configured to apply a calibration input signal at the RF-input and sense a resulting calibration output signal at the demodulator output to derive a gain of the mixing and amplification stage based on the relationship between the calibration output signal and the calibration input signal.

Abstract translation: RF解调器包括RF输入，解调器输出，耦合在RF输入和解调器输出之间的混合和放大级以及校准电路。 校准电路被配置为在RF输入处施加校准输入信号并且在解调器输出处感测产生的校准输出信号，以基于校准输出信号和校准输入之间的关系导出混合和放大级的增益 信号。

公开(公告)号：US08358998B2

公开(公告)日：2013-01-22

申请号：US12837807

申请日：2010-07-16

Applicant: Young-Ho Kim

Inventor： Young-Ho Kim

IPC: H04B1/26

CPC classification number: H03D7/1441 ,  H03D7/1408 ,  H03D7/1433 ,  H03D7/1458 ,  H03D2200/0025 ,  H03D2200/0033 ,  H03D2200/0043 ,  H03D2200/0084 ,  H03D2200/0096

Abstract: A down-conversion frequency mixer includes: a radio frequency (RF) input unit disposed between a VDD line and a GND line and configured to receive an RF signal; an LO input unit configured to receive a carrier frequency (LO) from an internal frequency synthesizer; an intermediate frequency (IF) output unit disposed in parallel to the RF input unit between the VDD line and the GND line and configured to mix the RF signal with the LO signal and output an IF signal; a current generation unit configured to generate a stabilized current without being influenced with noise entered through the VDD line and the GND line; and a noise blocking unit disposed between the VDD line and the RF input unit, between the VDD line and the IF output unit, between the GND line and the RF input unit, and between the GND line and the LO input unit and configured to copy the current generated from the current generator and generate a stabilized current.

Abstract translation: 下变频混频器包括：射频（RF）输入单元，设置在VDD线和GND线之间，并被配置为接收RF信号; LO输入单元，被配置为从内部频率合成器接收载波频率（LO）; 中频（IF）输出单元，其与VDD线和GND线之间的RF输入单元并联配置，并配置为将RF信号与LO信号混频并输出IF信号; 电流产生单元，被配置为产生稳定电流，而不受通过VDD线和GND线输入的噪声的影响; 以及噪声阻断单元，设置在VDD线和RF输入单元之间，VDD线和IF输出单元之间，GND线和RF输入单元之间，以及GND线和LO输入单元之间，并配置为复制 从电流发生器产生的电流产生稳定的电流。

公开(公告)号：US08280339B2

公开(公告)日：2012-10-02

申请号：US11621121

申请日：2007-01-09

Applicant: Ying-Hsi Lin

Inventor： Ying-Hsi Lin

IPC: H04B1/26

CPC classification number: H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03D2200/0025 ,  H03D2200/0033 ,  H03D2200/0043 ,  H03D2200/0088

Abstract: A mixer capable of detecting or controlling a common mode voltage thereof, includes at least: a mixing module for mixing a first set of differential signals and a second set of differential signals to generate at least one mixed signal; and a compensation module for compensating at least one operation point of the mixing module.

Abstract translation: 能够检测或控制其共模电压的混频器至少包括：混合模块，用于混合第一组差分信号和第二组差分信号以产生至少一个混合信号; 以及用于补偿混合模块的至少一个操作点的补偿模块。

公开(公告)号：US08275332B2

公开(公告)日：2012-09-25

申请号：US13303066

申请日：2011-11-22

Applicant: Ahmad Mirzaei ,  Alireza Zolfaghari ,  Hooman Darabi

Inventor： Ahmad Mirzaei ,  Alireza Zolfaghari ,  Hooman Darabi

IPC: H04B1/04

CPC classification number: H03G1/0029 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/165 ,  H03D2200/0025 ,  H03G1/0088

Abstract: An apparatus comprising a plurality of switchable full step mixer unit cells, wherein each switchable full step unit cell is configured to, when the full step transceiver mixer unit cell is turned on, increase the gain experienced by an electronic signal by a full step increment, and wherein the step increment is substantially constant regardless of temperature; and at least one switchable partial step mixer unit cell configured to, when the partial step transceiver mixer unit is turned on, increase the gain experienced by the electronic signal by a predetermined step increment less than that of a full step, and wherein the partial step increment is substantially constant regardless of temperature.

Abstract translation: 一种包括多个可切换全步骤混合器单位单元的装置，其中每个可切换全阶单元单元被配置为当全步进收发器混合器单元被接通时，增加电子信号经历的增益全步进增量， 并且其中所述阶梯增量基本上恒定，不管温度如何; 以及至少一个可切换部分步骤混合器单元，其被配置为当所述部分步骤收发器混合器单元被接通时，增加所述电子信号经历的增益小于完整步长的预定步长增量，并且其中所述部分步骤 无论温度如何，增量都是基本恒定的。

公开(公告)号：US20120071119A1

公开(公告)日：2012-03-22

申请号：US13303066

申请日：2011-11-22

Applicant: Ahmad Mirzaei ,  Alireza Zolfaghari ,  Hooman Darabi

Inventor： Ahmad Mirzaei ,  Alireza Zolfaghari ,  Hooman Darabi

IPC: H04B1/04

CPC classification number: H03G1/0029 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/165 ,  H03D2200/0025 ,  H03G1/0088

Abstract: An apparatus comprising a plurality of switchable full step mixer unit cells, wherein each switchable full step unit cell is configured to, when the full step transceiver mixer unit cell is turned on, increase the gain experienced by an electronic signal by a full step increment, and wherein the step increment is substantially constant regardless of temperature; and at least one switchable partial step mixer unit cell configured to, when the partial step transceiver mixer unit is turned on, increase the gain experienced by the electronic signal by a predetermined step increment less than that of a full step, and wherein the partial step increment is substantially constant regardless of temperature.

Abstract translation: 一种包括多个可切换全步骤混合器单位单元的装置，其中每个可切换全阶单元单元被配置为当全步进收发器混合器单元被接通时，增加电子信号经历的增益全步进增量， 并且其中所述阶梯增量基本上恒定，不管温度如何; 以及至少一个可切换部分步骤混合器单元，其被配置为当所述部分步骤收发器混合器单元被接通时，增加所述电子信号经历的增益小于完整步长的预定步长增量，并且其中所述部分步骤 无论温度如何，增量都是基本恒定的。

公开(公告)号：US08019312B2

公开(公告)日：2011-09-13

申请号：US12544499

申请日：2009-08-20

Applicant: Tzi-Hsiung Shu

Inventor： Tzi-Hsiung Shu

IPC: H04B1/10 ,  H04B1/26 ,  H04B15/00

CPC classification number: H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03D7/1483 ,  H03D7/165 ,  H03D2200/0025 ,  H03D2200/0043 ,  H03D2200/0047 ,  H04B1/30

Abstract: An apparatus, method, and system for DC offset cancellation are provided herein. For instance, the apparatus can include a first commutating mixer switch and a second commutating mixer switch. The first commutating mixer switch can have a first input port configured to receive a first differential signal and a first differential output port. The second commutating mixer switch can have a second input port configured to receive a second differential offset signal and a second differential output port. The first and second differential output ports can be coupled to one another to provide a combined differential output signal.

Abstract translation: 本文提供了一种用于DC偏移消除的装置，方法和系统。 例如，该装置可以包括第一换向混合开关和第二换向混合开关。 第一整流混频器开关可以具有被配置为接收第一差分信号和第一差分输出端口的第一输入端口。 第二整流混频器开关可以具有被配置为接收第二差分偏移信号的第二输入端口和第二差分输出端口。 第一和第二差分输出端口可以彼此耦合以提供组合的差分输出信号。

公开(公告)号：US07902937B2

公开(公告)日：2011-03-08

申请号：US12534294

申请日：2009-08-03

Applicant: Fenghao Mu

Inventor： Fenghao Mu

IPC: H04L27/20

CPC classification number: H03D7/1441 ,  H03D7/1458 ,  H03D7/1491 ,  H03D7/165 ,  H03D7/166 ,  H03D2200/0025 ,  H03D2200/0084 ,  H03D2200/009

Abstract: A differential positive coefficient weighted quadrature modulator is actuated responsive to quadrature clock signals and positive digital modulation signals input to the modulator. The modulator includes an I-channel positive coefficient weighted modulator (PCWM) and a Q-channel PCWM. The I-channel PCWM has differential output nodes configured to output a differential I-channel signal responsive to the state of first and second positive digital modulation signals and first and second complimentary quadrature clock signals input to the I-channel PCWM. The Q-channel PCWM has differential output nodes configured to output a differential Q-channel signal responsive to the state of third and fourth positive digital modulation signals and third and fourth complimentary quadrature clock signals input to the Q-channel PCWM. The positive digital modulation signals input to the I-channel and Q-channel PCWMs have positive amplitude and the I-channel and Q-channel PCWMs conduct at approximately half clock cycle or less of the corresponding quadrature clock signals.

Abstract translation: 响应于输入到调制器的正交时钟信号和正数字调制信号，启动差分正系数加权正交调制器。 调制器包括I通道正系数加权调制器（PCWM）和Q通道PCWM。 I信道PCWM具有差分输出节点，其被配置为响应于第一和第二正数字调制信号的状态以及输入到I信道PCWM的第一和第二互补正交时钟信号来输出差分I信道信号。 Q通道PCWM具有差分输出节点，其被配置为响应于输入到Q通道PCWM的第三和第四正数字调制信号以及第三和第四互补正交时钟信号的状态输出差分Q信道信号。 输入到I信道和Q信道PCWM的正数字调制信号具有正振幅，并且I信道和Q信道PCWM在相应的正交时钟信号的大约半个时钟周期或更短周期内传导。