公开(公告)号：US11784245B2

公开(公告)日：2023-10-10

申请号：US17002618

申请日：2020-08-25

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenji Sasaki ,  Yasunari Umemoto ,  Shigeki Koya ,  Shinnosuke Takahashi ,  Masao Kondo

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/08 ,  H01L29/205 ,  H01L29/417 ,  H01L27/02 ,  H01L23/528 ,  H03K17/60 ,  H01L23/00 ,  H03F3/189

CPC classification number: H01L29/7371 ,  H01L23/5286 ,  H01L24/13 ,  H01L27/0229 ,  H01L29/0692 ,  H01L29/0826 ,  H01L29/205 ,  H01L29/41708 ,  H03K17/602 ,  H03F3/189 ,  H03F2200/222 ,  H03F2200/318 ,  H03F2200/387 ,  H03F2200/451

Abstract: An electrically conductive sub-collector layer is provided in a surface layer portion of a substrate. A collector layer, a base layer, and an emitter layer are located within the sub-collector layer when viewed in plan. The collector layer is connected to the sub-collector layer. An emitter electrode and a base electrode are long in a first direction when viewed in plan. The emitter electrode overlaps the emitter layer. The base electrode and the emitter electrode are discretely located away from each other in a second direction orthogonal to the first direction. A collector electrode is located on one side in the second direction with respect to the emitter electrode and is not located on the other side when viewed in plan. A base line is connected to the base electrode in a manner so as to adjoin a portion other than longitudinal ends of the base electrode.

公开(公告)号：US11631758B2

公开(公告)日：2023-04-18

申请号：US16810492

申请日：2020-03-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Isao Obu ,  Kaoru Ideno ,  Shigeki Koya

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/737

Abstract: A semiconductor device includes a collector layer, a base layer, and an emitter layer that are disposed above a substrate. An emitter mesa layer is disposed on a partial region of the emitter layer. In a plan view, the base electrode is disposed in or on a region which does not overlap the emitter mesa layer. The base electrode allows base current to flow to the base layer. In the plan view, a first edge forming part of edges of the emitter mesa layer extends in a first direction, and a second edge forming part of edges of the base electrode faces the first edge. A gap between the first edge and the second edge in a terminal portion located in an end portion of the emitter mesa layer in the first direction is wider than a gap in an intermediate portion of the emitter mesa layer.

公开(公告)号：US11476807B2

公开(公告)日：2022-10-18

申请号：US17082990

申请日：2020-10-28

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shigeki Koya ,  Takayuki Tsutsui ,  Yasunari Umemoto ,  Isao Obu ,  Satoshi Tanaka

IPC: H03F1/32 ,  H03F3/21 ,  H03F3/19 ,  H03G3/00 ,  H03F1/56 ,  H03F1/02 ,  H03G3/30 ,  H03F3/24

Abstract: A power amplifier module includes a first amplifier circuit that amplifies a radio frequency signal with a first gain corresponding to a first control signal to generate a first amplified signal; a second amplifier circuit that amplifies the first amplified signal with a second gain corresponding to a second control signal to generate a second amplified signal; and a control unit that generates the first control signal and the second control signal. The second control signal is a control signal for increasing a power-supply voltage for the second amplifier circuit as a peak-to-average power ratio of the radio frequency signal increases. The first control signal is a control signal for controlling the first gain of the first amplifier circuit so that a variation in the second gain involved in a variation in the power-supply voltage for the second amplifier circuit is compensated for.

公开(公告)号：US10923470B2

公开(公告)日：2021-02-16

申请号：US16826074

申请日：2020-03-20

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shigeki Koya ,  Takayuki Tsutsui ,  Kazuhito Nakai ,  Yusuke Tanaka

IPC: H01L27/06 ,  H01L23/522 ,  H01L23/528 ,  H01L29/66

Abstract: A semiconductor device includes a plurality of unit transistors that are arranged on a surface of a substrate in a first direction. Input capacitive elements are arranged so as to correspond to the unit transistors. An emitter common wiring line is connected to emitter layers of the unit transistors. A via-hole extending from the emitter common wiring line to a back surface of the substrate is disposed at a position overlapping the emitter common wiring line. A collector common wiring line is connected to collector layers of the unit transistors. The input capacitive elements, the emitter common wiring line, the unit transistors, and the collector common wiring line are arranged in this order in a second direction. Base wiring lines that connect the input capacitive elements to base layers of the corresponding unit transistors intersect the emitter common wiring line without physical contact.

公开(公告)号：US10886388B2

公开(公告)日：2021-01-05

申请号：US16822889

申请日：2020-03-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Shigeki Koya ,  Isao Obu

IPC: H01L29/73 ,  H01L29/737 ,  H01L29/66 ,  H01L29/08 ,  H01L29/205

Abstract: A collector layer of an HBT includes a high-concentration collector layer and a low-concentration collector layer thereon. The low-concentration collector layer includes a graded collector layer in which the energy band gap varies to narrow with increasing distance from the base layer. The electron affinity of the semiconductor material for the base layer is greater than that of the semiconductor material for the graded collector layer at the point of the largest energy band gap by about 0.15 eV or less. The electron velocity in the graded collector layer peaks at a certain electric field strength. In the graded collector layer, the strength of the quasi-electric field, an electric field that acts on electrons as a result of the varying energy band gap, is between about 0.3 times and about 1.8 times the peak electric field strength, the electric field strength at which the electron velocity peaks.

公开(公告)号：US10777669B2

公开(公告)日：2020-09-15

申请号：US16152285

申请日：2018-10-04

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Shigeki Koya ,  Isao Obu

IPC: H01L29/737 ,  H01L29/205 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L21/285 ,  H01L21/308 ,  H01L21/306 ,  H03F3/21

Abstract: A heterojunction bipolar transistor includes a collector layer, a base layer, and an emitter layer that are stacked on a substrate. The collector layer includes a graded semiconductor layer in which an electron affinity increases from a side closer to the base layer toward a side farther from the base layer. An electron affinity of the base layer at an interface closer to the collector layer is equal to an electron affinity of the graded semiconductor layer at an interface closer to the base layer.

公开(公告)号：US10523161B2

公开(公告)日：2019-12-31

申请号：US15995202

申请日：2018-06-01

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shigeki Koya

IPC: H03F3/191 ,  H03F1/56 ,  H03F1/02 ,  H03F3/19 ,  H03F3/21 ,  H03F1/32 ,  H03F3/217 ,  H03F3/24

Abstract: A power amplification module includes: an amplifier that amplifies an input signal and outputs an amplified signal; and a harmonic-termination circuit to which harmonics of the amplified signal are input and the impedance of which is controlled in accordance with the frequency of a harmonic. The power amplification module can operate in a first mode in which a power supply voltage changes in accordance with the average voltage value of the amplified signal over a prescribed time period or in a second mode in which the power supply voltage changes in accordance with the envelope of the input signal. The impedance of the harmonic-termination circuit is controlled such that at least one even-ordered harmonic is short-circuited when the power amplification module operates in the first mode and at least one odd-ordered harmonic of third order or higher is short-circuited when the power amplification module operates in the second mode.

公开(公告)号：US11984380B2

公开(公告)日：2024-05-14

申请号：US17370953

申请日：2021-07-08

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masao Kondo ,  Kenji Sasaki ,  Shigeki Koya

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/055 ,  H01L23/31 ,  H01L23/42 ,  H01L23/498 ,  H01L25/18 ,  H05K1/11 ,  H05K1/18

CPC classification number: H01L23/3675 ,  H01L23/055 ,  H01L23/3121 ,  H01L23/42 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L25/18 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H01L2224/16227

Abstract: A semiconductor package includes a module substrate having opposite top and bottom surfaces, a semiconductor chip provided with bumps and mounted on the top surface of the module substrate via the bumps, and a metal member having a top portion disposed at a level higher than the semiconductor chip with reference to the top surface of the module substrate and including the semiconductor chip in plan view and a side portion extending from the top portion toward the module substrate. The module substrate includes a first metal film disposed on or in at least one of the bottom surface and an internal layer of the module substrate. The first metal film is electrically connected to the bumps and reaches a side surface of the module substrate. The side portion is thermally coupled to the first metal film at the side surface of the module substrate.

公开(公告)号：US11830917B2

公开(公告)日：2023-11-28

申请号：US17027618

申请日：2020-09-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Shaojun Ma ,  Shigeki Koya

IPC: H03F3/14 ,  H01L29/423 ,  H03F3/21 ,  H03F1/02 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/737

CPC classification number: H01L29/42304 ,  H01L27/0658 ,  H01L29/0817 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/7371 ,  H03F1/0205 ,  H03F3/21 ,  H03F2200/451

Abstract: A collector layer is disposed on a substrate. The collector layer is a continuous region when viewed in plan. A base layer is disposed on the collector layer. An emitter layer is disposed on the base layer. An emitter mesa layer is disposed on the emitter layer. Two base electrodes are located outside the emitter mesa layer and within the base layer when viewed in plan. The two base electrodes are electrically connected to the base layer. Two capacitors are disposed on or above the substrate. Each of the two capacitors is connected between a corresponding one of the two base electrodes and a first line above the substrate. Two resistance elements are disposed on or above the substrate. Each of the two resistance elements is connected between a corresponding one of the two base electrodes and a second line on or above the substrate.

公开(公告)号：US11626511B2

公开(公告)日：2023-04-11

申请号：US16207084

申请日：2018-11-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao Obu ,  Yasunari Umemoto ,  Masahiro Shibata ,  Shigeki Koya ,  Masao Kondo ,  Takayuki Tsutsui

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L21/02 ,  H01L21/285 ,  H01L21/308 ,  H01L21/306 ,  H01L29/66 ,  H01L23/00

Abstract: A bipolar transistor including a first collector layer, a second collector layer, a base layer, and an emitter layer is disposed on a substrate. Etching characteristics of the second collector layer are different from etching characteristics of the first collector layer and the base layer. In plan view, an edge of an interface between the first collector layer and the second collector layer is disposed inside an edge of a lower surface of the base layer, and an edge of an upper surface of the second collector layer coincides with the edge of the lower surface of the base layer or is disposed inside the edge of the lower surface of the base layer.