公开(公告)号：US11626511B2

公开(公告)日：2023-04-11

申请号：US16207084

申请日：2018-11-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao Obu ,  Yasunari Umemoto ,  Masahiro Shibata ,  Shigeki Koya ,  Masao Kondo ,  Takayuki Tsutsui

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L21/02 ,  H01L21/285 ,  H01L21/308 ,  H01L21/306 ,  H01L29/66 ,  H01L23/00

Abstract: A bipolar transistor including a first collector layer, a second collector layer, a base layer, and an emitter layer is disposed on a substrate. Etching characteristics of the second collector layer are different from etching characteristics of the first collector layer and the base layer. In plan view, an edge of an interface between the first collector layer and the second collector layer is disposed inside an edge of a lower surface of the base layer, and an edge of an upper surface of the second collector layer coincides with the edge of the lower surface of the base layer or is disposed inside the edge of the lower surface of the base layer.

公开(公告)号：US11469187B2

公开(公告)日：2022-10-11

申请号：US16943243

申请日：2020-07-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiroaki Tokuya ,  Masahiro Shibata ,  Akihiko Ozaki ,  Satoshi Goto ,  Fumio Harima ,  Atsushi Kurokawa

IPC: H01L29/737 ,  H01L27/082 ,  H01L23/498 ,  H01L23/66 ,  H01L23/00

Abstract: At least one unit transistor is arranged over a substrate. A first wiring as a path of current that flows to each unit transistor is arranged over the at least one unit transistor. An inorganic insulation film is arranged over the first wiring. At least one first opening overlapping a partial region of the first wiring in a plan view is provided in the inorganic insulation film. An organic insulation film is arranged over the inorganic insulation film. A second wiring coupled to the first wiring through the first opening is arranged over the organic insulation film and the inorganic insulation film. In a plan view, a region in which the organic insulation film is not arranged is provided outside a region in which the first wiring is arranged. The second wiring is in contact with the inorganic insulation film outside the region in which the first wiring is arranged.

公开(公告)号：US10665704B2

公开(公告)日：2020-05-26

申请号：US16125234

申请日：2018-09-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao Obu ,  Yasunari Umemoto ,  Masahiro Shibata ,  Shigeki Koya ,  Masao Kondo ,  Takayuki Tsutsui

IPC: H01L29/737 ,  H01L23/00 ,  H03F3/24 ,  H03F1/56 ,  H01L29/205 ,  H03F3/195 ,  H03F3/213 ,  H01L21/308 ,  H01L21/311 ,  H01L21/285 ,  H01L21/02 ,  H01L21/306 ,  H01L29/423 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10 ,  H03F1/30 ,  H01L29/45 ,  H01L29/735 ,  H01L27/102 ,  H01L29/66 ,  H03F3/21

Abstract: A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.

公开(公告)号：US10594271B2

公开(公告)日：2020-03-17

申请号：US16435321

申请日：2019-06-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao Obu ,  Yasunari Umemoto ,  Masahiro Shibata ,  Kenichi Nagura

IPC: H03F1/52 ,  H01L23/00 ,  H01L29/04 ,  H03F3/213 ,  H01L29/737 ,  H01L27/02 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L29/06 ,  H01L21/265 ,  H01L29/417 ,  H01L29/423 ,  H01L23/48 ,  H01L29/861 ,  H01L21/768 ,  H03F3/195 ,  H01L21/02 ,  H01L29/36 ,  H01L29/207 ,  H01L29/45 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/027 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311 ,  H03F1/56 ,  H01L23/31 ,  H01L23/29 ,  H01L23/538 ,  H01L25/16 ,  H01L21/8252

Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

公开(公告)号：US11948986B2

公开(公告)日：2024-04-02

申请号：US17348811

申请日：2021-06-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Atsushi Kurokawa ,  Masahiro Shibata ,  Hiroaki Tokuya ,  Mari Saji

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/73

CPC classification number: H01L29/41708 ,  H01L29/0817 ,  H01L29/73

Abstract: A mesa portion is formed on a substrate. An insulating film including an organic layer is disposed on the mesa portion. A conductor film is disposed on the insulating film. A cavity provided in the organic layer has side surfaces extending in a first direction. A shorter distance out of distances in a second direction perpendicular to the first direction from the mesa portion to the side surfaces of the cavity in plan view is defined as a first distance. A shorter distance out of distances in the first direction from the mesa portion to side surfaces of the cavity in plan view is defined as a second distance. A height of a first step of the mesa portion is defined as a first height. At least one of the first distance and the second distance is greater than or equal to the first height.

公开(公告)号：US10903803B2

公开(公告)日：2021-01-26

申请号：US16785482

申请日：2020-02-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao Obu ,  Yasunari Umemoto ,  Masahiro Shibata ,  Kenichi Nagura

IPC: H01L29/06 ,  H03F1/52 ,  H01L23/00 ,  H01L29/04 ,  H03F3/213 ,  H01L29/737 ,  H01L27/02 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L21/265 ,  H01L29/417 ,  H01L29/423 ,  H01L23/48 ,  H01L29/861 ,  H01L21/768 ,  H03F3/195 ,  H01L21/02 ,  H01L29/36 ,  H01L29/207 ,  H01L29/45 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/027 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311 ,  H03F1/56 ,  H01L23/31 ,  H01L23/29 ,  H01L23/538 ,  H01L25/16 ,  H01L21/8252

Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

公开(公告)号：US20180240725A1

公开(公告)日：2018-08-23

申请号：US15899010

申请日：2018-02-19

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao Obu ,  Yasunari Umemoto ,  Masahiro Shibata

IPC: H01L23/31 ,  H01L23/495 ,  H01L23/00 ,  H01L21/56 ,  H01L21/52 ,  H01L21/67

Abstract: A semiconductor chip includes a single-crystal substrate and a metal electrode on the bottom surface of the substrate. The metal electrode has a region in which a first metal is exposed and a region in which a second metal is exposed, the second metal having a standard electrode potential different from that of the first metal.

公开(公告)号：US11652016B2

公开(公告)日：2023-05-16

申请号：US17345581

申请日：2021-06-11

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Mari Saji ,  Masahiro Shibata ,  Atsushi Kurokawa

IPC: H01L23/36 ,  H01L23/48 ,  H01L23/00 ,  H01L29/737 ,  H01L29/205 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L23/36 ,  H01L23/481 ,  H01L24/14 ,  H01L29/737

Abstract: A first layer conductor film is connected to an operation electrode through an opening in a first layer interlayer insulating film. An opening in a second layer interlayer insulating film is encompassed by the first layer conductor film in plan view. A second layer conductor film is connected to the first layer conductor film through the opening in a second layer interlayer insulating film. The average, along a first direction, of distances in a second direction, which is perpendicular to the first direction, from the opening in the first layer interlayer insulating film to the side surface of the opening in the second layer interlayer insulating film is greater than or equal to a distance in a height direction from an upper opening plane of the opening in the first layer interlayer insulating film to a lower opening plane of the opening in the second layer interlayer insulating film.

公开(公告)号：US11621678B2

公开(公告)日：2023-04-04

申请号：US17143940

申请日：2021-01-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao Obu ,  Yasunari Umemoto ,  Masahiro Shibata ,  Kenichi Nagura

IPC: H03F1/52 ,  H01L23/00 ,  H01L29/04 ,  H03F3/213 ,  H01L29/737 ,  H01L27/02 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L29/06 ,  H01L21/265 ,  H01L29/417 ,  H01L29/423 ,  H01L23/48 ,  H01L29/861 ,  H01L21/768 ,  H03F3/195 ,  H01L21/02 ,  H01L29/36 ,  H01L29/207 ,  H01L29/45 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/027 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311 ,  H03F1/56 ,  H01L23/31 ,  H01L23/29 ,  H01L23/538 ,  H01L25/16 ,  H01L21/8252

Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

公开(公告)号：US11502016B2

公开(公告)日：2022-11-15

申请号：US17081833

申请日：2020-10-27

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masao Kondo ,  Masahiro Shibata

IPC: H01L23/367 ,  H01L29/737 ,  H01L29/417 ,  H01L23/498 ,  H01L23/00 ,  H03F3/21 ,  H03F1/30 ,  H01L29/06 ,  H03F3/213 ,  H03F3/195

Abstract: A power amplifier module includes a substrate including, in an upper surface of the substrate, an active region and an element isolation region. The power amplifier module further includes a collector layer, a base layer, and an emitter layer that are stacked on the active region; an interlayer insulating film that covers the collector layer, the base layer, and the emitter layer; a pad that is thermally coupled to the element isolation region; and an emitter bump that is disposed on the interlayer insulating film, electrically connected to the emitter layer through a via hole provided in the interlayer insulating film, and electrically connected to the pad. In plan view, the emitter bump partially overlaps an emitter region which is a region of the emitter layer and through which an emitter current flows.