公开(公告)号：US12040323B2

公开(公告)日：2024-07-16

申请号：US17394252

申请日：2021-08-04

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Shaojun Ma ,  Shigeki Koya ,  Kenji Sasaki

IPC: H01L27/06 ,  H01L29/737 ,  H03F3/19 ,  H03F3/21

CPC classification number: H01L27/0647 ,  H01L29/737 ,  H03F3/19 ,  H03F3/21

Abstract: Each of cells arranged on a substrate surface along a first direction includes at least one unit transistor. Collector electrodes are arranged between two adjacent cells. A first cell, which is at least one of the cells, includes unit transistors arranged along the first direction. The unit transistors are connected in parallel to each another. In the first cell, the base electrode and the emitter electrode in each unit transistor are arranged along the first direction, and the order of arrangement of the base electrode and the emitter electrode is the same among the unit transistors. When looking at one first cell, a maximum value of distances in the first direction between the emitter electrodes of two adjacent unit transistors in the first cell being looked at is shorter than ½ of a shorter one of distances between the first cell being looked at and adjacent cells.

公开(公告)号：US11990873B2

公开(公告)日：2024-05-21

申请号：US17168904

申请日：2021-02-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Shaojun Ma ,  Shigeki Koya

IPC: H03F1/30 ,  H03F3/19 ,  H03F3/21

CPC classification number: H03F1/302 ,  H03F3/19 ,  H03F3/211 ,  H03F2200/451

Abstract: A first amplifier circuit in a preceding stage, a second amplifier circuit in a subsequent stage, and a ground external connection terminal are disposed on a substrate. The first and second amplifier circuits each include bipolar transistors, capacitive elements for the respective bipolar transistors, and resistive elements for the respective bipolar transistors. The bipolar transistors each include separate base electrodes, that is, a first base electrode for radio frequency and a second base electrode for biasing. The bipolar transistors of the second amplifier circuit include emitter electrodes connected to the ground external connection terminal. The minimum spacing between the first base electrode and an emitter mesa layer of at least one of the bipolar transistors of the second amplifier circuit is greater than the minimum spacing between the first base electrode and am emitter mesa layer of each of the bipolar transistors of the first amplifier circuit.

公开(公告)号：US11894365B2

公开(公告)日：2024-02-06

申请号：US17216404

申请日：2021-03-29

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shaojun Ma ,  Yasunari Umemoto ,  Kenji Sasaki

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/205 ,  H01L29/737 ,  H01L23/66

CPC classification number: H01L27/0658 ,  H01L23/66 ,  H01L28/20 ,  H01L28/60 ,  H01L29/205 ,  H01L29/7371 ,  H03F2200/451

Abstract: Multiple bipolar transistors are disposed side by side in the first direction on a substrate. Multiple first capacitance devices are provided corresponding to the respective base electrodes of the bipolar transistors. A radio frequency signal is supplied to the bipolar transistors through the first capacitance devices. Resistive devices are provided corresponding to the respective base electrodes of the bipolar transistors. A base bias is supplied to the bipolar transistors through the resistive devices. The first capacitance devices are disposed on the same side relative to the second direction orthogonal to the first direction, when viewed from the bipolar transistors. At least one of the first capacitance devices is disposed so as to overlap another first capacitance device partially when viewed in the second direction from the bipolar transistors.

公开(公告)号：US11830917B2

公开(公告)日：2023-11-28

申请号：US17027618

申请日：2020-09-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Shaojun Ma ,  Shigeki Koya

IPC: H03F3/14 ,  H01L29/423 ,  H03F3/21 ,  H03F1/02 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/737

CPC classification number: H01L29/42304 ,  H01L27/0658 ,  H01L29/0817 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/7371 ,  H03F1/0205 ,  H03F3/21 ,  H03F2200/451

Abstract: A collector layer is disposed on a substrate. The collector layer is a continuous region when viewed in plan. A base layer is disposed on the collector layer. An emitter layer is disposed on the base layer. An emitter mesa layer is disposed on the emitter layer. Two base electrodes are located outside the emitter mesa layer and within the base layer when viewed in plan. The two base electrodes are electrically connected to the base layer. Two capacitors are disposed on or above the substrate. Each of the two capacitors is connected between a corresponding one of the two base electrodes and a first line above the substrate. Two resistance elements are disposed on or above the substrate. Each of the two resistance elements is connected between a corresponding one of the two base electrodes and a second line on or above the substrate.