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    Stacked fan-out package structure
    11.
    发明授权
    Stacked fan-out package structure 有权

    公开(公告)号：US10692789B2

    公开(公告)日：2020-06-23

    申请号：US15968449

    申请日：2018-05-01

    Applicant: MediaTek Inc.

    Inventor： Nai-Wei Liu ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Ching-Wen Hsiao ,  Wei-Che Huang

    IPC: H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56

    Abstract: A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on the second surface of the first semiconductor die and laterally extends on the first molding compound. A second semiconductor die is disposed on the first RDL structure and has a first surface and a second surface opposite thereto. A second molding compound surrounds the second semiconductor die. A first protective layer covers a sidewall of the first RDL structure and a sidewall of the first molding compound.

    STACKED FAN-OUT PACKAGE STRUCTURE
    13.
    发明申请
    STACKED FAN-OUT PACKAGE STRUCTURE 审中-公开

    公开(公告)号：US20180323127A1

    公开(公告)日：2018-11-08

    申请号：US15968449

    申请日：2018-05-01

    Applicant: MediaTek Inc.

    Inventor： Nai-Wei Liu ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Ching-Wen Hsiao ,  Wei-Che Huang

    IPC: H01L23/31 ,  H01L23/00 ,  H01L23/538

    Abstract: A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on the second surface of the first semiconductor die and laterally extends on the first molding compound. A second semiconductor die is disposed on the first RDL structure and has a first surface and a second surface opposite thereto. A second molding compound surrounds the second semiconductor die. A first protective layer covers a sidewall of the first RDL structure and a sidewall of the first molding compound.

    Semiconductor package assembly with through silicon via interconnect
    17.
    发明授权
    Semiconductor package assembly with through silicon via interconnect 有权
    半导体封装组件通过硅芯片通过互连

    公开(公告)号：US09570399B2

    公开(公告)日：2017-02-14

    申请号：US14963451

    申请日：2015-12-09

    Applicant: MediaTek Inc.

    Inventor： Ming-Tzong Yang ,  Cheng-Chou Hung ,  Wei-Che Huang ,  Yu-Hua Huang ,  Tzu-Hung Lin ,  Kuei-Ti Chan ,  Ruey-Beei Wu ,  Kai-Bin Wu

    IPC: H01L23/538 ,  H01L25/065 ,  H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00

    CPC classification number: H01L23/5384 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/14 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2225/06541 ,  H01L2225/06544

    Abstract: The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor die mounted on a base. The first semiconductor die includes a semiconductor substrate. A first array of TSV interconnects and a second array of TSV interconnects are formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. A first ground TSV interconnect is disposed within the interval region. A second semiconductor die is mounted on the first semiconductor die, having a ground pad thereon. The first ground TSV interconnect of the first semiconductor die has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.

    Abstract translation: 本发明提供一种具有TSV互连的半导体封装组件。 半导体封装组件包括安装在基座上的第一半导体管芯。 第一半导体管芯包括半导体衬底。 通过半导体衬底形成TSV互连的第一阵列和TSV互连的第二阵列，其中TSV互连的第一阵列和第二阵列被间隔区隔开。 第一接地TSV互连设置在间隔区域内。 第二半导体管芯安装在第一半导体管芯上，其上具有接地焊盘。 第一半导体管芯的第一接地TSV互连具有耦合到第二半导体管芯的接地焊盘的第一端子和耦合到布置在半导体衬底的前侧上的互连结构的第二端子。

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