公开(公告)号：US12272755B2

公开(公告)日：2025-04-08

申请号：US18420327

申请日：2024-01-23

Applicant: MediaTek Inc.

Inventor： Cheng-Tien Wan ,  Ming-Cheng Lee

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

Abstract: A semiconductor structure includes several semiconductor stacks over a substrate, and each of the semiconductor stacks extends in a first direction, wherein adjacent semiconductor stacks are spaced apart from each other in a second direction, which is different from the first direction. Each of the semiconductor stacks includes channel layers above the substrate and a gate structure across the channel layers. The channel layers are spaced apart from each other in the third direction. The gate structure includes gate dielectric layers around the respective channel layers, and a gate electrode along sidewalls of the gate dielectric layers and a top surface of the uppermost gate dielectric layer. The space in the third direction between the two lowermost channel layers is greater than the space in the third direction between the two uppermost channel layers in the same semiconductor stack.

公开(公告)号：US11916108B2

公开(公告)日：2024-02-27

申请号：US18161181

申请日：2023-01-30

Applicant: MediaTek Inc.

Inventor： Cheng-Tien Wan ,  Ming-Cheng Lee

IPC: H01L21/8238 ,  H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor fin over a substrate, and a gate structure along sidewalls and the top surface of the semiconductor fin. The gate structure covers the first portion of the semiconductor fin. The semiconductor device also includes a source/drain feature adjacent to the gate structure. The semiconductor device further includes a source/drain contact connected to the source/drain feature. The source/drain contact extends downwards to a position that is lower than the top surface of the first portion of the semiconductor fin.

公开(公告)号：US11600700B2

公开(公告)日：2023-03-07

申请号：US17513819

申请日：2021-10-28

Applicant: MediaTek Inc.

Inventor： Cheng-Tien Wan ,  Ming-Cheng Lee

IPC: H01L21/8238 ,  H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor fin over a substrate, and a gate structure along sidewalls and the top surface of the semiconductor fin. The gate structure covers the first portion of the semiconductor fin. The semiconductor device also includes a source/drain feature adjacent to the gate structure. The semiconductor device further includes a source/drain contact connected to the source/drain feature. The source/drain contact extends downwards to a position that is lower than the top surface of the first portion of the semiconductor fin.

公开(公告)号：US11189694B2

公开(公告)日：2021-11-30

申请号：US16590053

申请日：2019-10-01

Applicant: MediaTek Inc.

Inventor： Cheng-Tien Wan ,  Ming-Cheng Lee

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor fin over a substrate, and a gate structure along sidewalls and the top surface of the semiconductor fin. The gate structure covers the first portion of the semiconductor fin. The semiconductor device also includes a source/drain feature adjacent to the gate structure. The semiconductor device further includes a source/drain contact connected to the source/drain feature. The source/drain contact extends downwards to a position that is lower than the top surface of the first portion of the semiconductor fin.

公开(公告)号：US12237401B2

公开(公告)日：2025-02-25

申请号：US17821195

申请日：2022-08-22

Applicant: MEDIATEK Inc.

Inventor： Cheng-Tien Wan ,  Yao-Tsung Huang ,  Yun-San Huang ,  Ming-Cheng Lee ,  Wei-Che Huang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.

公开(公告)号：US20240170580A1

公开(公告)日：2024-05-23

申请号：US18420327

申请日：2024-01-23

Applicant: MediaTek Inc.

Inventor： Cheng-Tien Wan ,  Ming-Cheng Lee

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02603 ,  H01L21/28255 ,  H01L21/28264 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78681 ,  H01L29/78684

Abstract: A semiconductor structure includes several semiconductor stacks over a substrate, and each of the semiconductor stacks extends in a first direction, wherein adjacent semiconductor stacks are spaced apart from each other in a second direction, which is different from the first direction. Each of the semiconductor stacks includes channel layers above the substrate and a gate structure across the channel layers. The channel layers are spaced apart from each other in the third direction. The gate structure includes gate dielectric layers around the respective channel layers, and a gate electrode along sidewalls of the gate dielectric layers and a top surface of the uppermost gate dielectric layer. The space in the third direction between the two lowermost channel layers is greater than the space in the third direction between the two uppermost channel layers in the same semiconductor stack.

公开(公告)号：US11450756B2

公开(公告)日：2022-09-20

申请号：US17001784

申请日：2020-08-25

Applicant: MEDIATEK Inc.

Inventor： Cheng-Tien Wan ,  Yao-Tsung Huang ,  Yun-San Huang ,  Ming-Cheng Lee ,  Wei-Che Huang

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.

公开(公告)号：US10790380B2

公开(公告)日：2020-09-29

申请号：US16121730

申请日：2018-09-05

Applicant: MEDIATEK Inc.

Inventor： Cheng-Tien Wan ,  Yao-Tsung Huang ,  Yun-San Huang ,  Ming-Cheng Lee ,  Wei-Che Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.

公开(公告)号：US11923460B2

公开(公告)日：2024-03-05

申请号：US17852292

申请日：2022-06-28

Applicant: MediaTek Inc.

Inventor： Cheng-Tien Wan ,  Ming-Cheng Lee

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02603 ,  H01L21/28255 ,  H01L21/28264 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78681 ,  H01L29/78684

Abstract: A semiconductor structure includes several semiconductor stacks over a substrate, and each of the semiconductor stacks extends in a first direction, wherein adjacent semiconductor stacks are spaced apart from each other in a second direction, which is different from the first direction. Each of the semiconductor stacks includes channel layers above the substrate and a gate structure across the channel layers. The channel layers are spaced apart from each other in the third direction. The gate structure includes gate dielectric layers around the respective channel layers, and a gate electrode along sidewalls of the gate dielectric layers and a top surface of the uppermost gate dielectric layer. The space in the third direction between the two lowermost channel layers is greater than the space in the third direction between the two uppermost channel layers in the same semiconductor stack.

公开(公告)号：US20220336680A1

公开(公告)日：2022-10-20

申请号：US17852292

申请日：2022-06-28

Applicant: MediaTek Inc.

Inventor： Cheng-Tien Wan ,  Ming-Cheng Lee

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

Abstract: A semiconductor structure includes several semiconductor stacks over a substrate, and each of the semiconductor stacks extends in a first direction, wherein adjacent semiconductor stacks are spaced apart from each other in a second direction, which is different from the first direction. Each of the semiconductor stacks includes channel layers above the substrate and a gate structure across the channel layers. The channel layers are spaced apart from each other in the third direction. The gate structure includes gate dielectric layers around the respective channel layers, and a gate electrode along sidewalls of the gate dielectric layers and a top surface of the uppermost gate dielectric layer. The space in the third direction between the two lowermost channel layers is greater than the space in the third direction between the two uppermost channel layers in the same semiconductor stack.