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    SEMICONDUCTOR STRUCTURE
    2.
    发明申请
    SEMICONDUCTOR STRUCTURE 有权

    公开(公告)号：US20220336680A1

    公开(公告)日：2022-10-20

    申请号：US17852292

    申请日：2022-06-28

    Applicant: MediaTek Inc.

    Inventor： Cheng-Tien Wan ,  Ming-Cheng Lee

    IPC: H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

    Abstract: A semiconductor structure includes several semiconductor stacks over a substrate, and each of the semiconductor stacks extends in a first direction, wherein adjacent semiconductor stacks are spaced apart from each other in a second direction, which is different from the first direction. Each of the semiconductor stacks includes channel layers above the substrate and a gate structure across the channel layers. The channel layers are spaced apart from each other in the third direction. The gate structure includes gate dielectric layers around the respective channel layers, and a gate electrode along sidewalls of the gate dielectric layers and a top surface of the uppermost gate dielectric layer. The space in the third direction between the two lowermost channel layers is greater than the space in the third direction between the two uppermost channel layers in the same semiconductor stack.

    Semiconductor structure
    3.
    发明授权
    Semiconductor structure 有权

    公开(公告)号：US12272755B2

    公开(公告)日：2025-04-08

    申请号：US18420327

    申请日：2024-01-23

    Applicant: MediaTek Inc.

    Inventor： Cheng-Tien Wan ,  Ming-Cheng Lee

    IPC: H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

    Abstract: A semiconductor structure includes several semiconductor stacks over a substrate, and each of the semiconductor stacks extends in a first direction, wherein adjacent semiconductor stacks are spaced apart from each other in a second direction, which is different from the first direction. Each of the semiconductor stacks includes channel layers above the substrate and a gate structure across the channel layers. The channel layers are spaced apart from each other in the third direction. The gate structure includes gate dielectric layers around the respective channel layers, and a gate electrode along sidewalls of the gate dielectric layers and a top surface of the uppermost gate dielectric layer. The space in the third direction between the two lowermost channel layers is greater than the space in the third direction between the two uppermost channel layers in the same semiconductor stack.

    METHOD FOR FABRICATING AN ESD PROTECTION DEVICE
    5.
    发明申请
    METHOD FOR FABRICATING AN ESD PROTECTION DEVICE 审中-公开
    制造防静电装置的方法

    公开(公告)号：US20140199818A1

    公开(公告)日：2014-07-17

    申请号：US14218991

    申请日：2014-03-19

    Applicant: MEDIATEK INC.

    Inventor： Ming-Tzong Yang ,  Ming-Cheng Lee

    IPC: H01L29/66 ,  H01L21/265

    CPC classification number: H01L29/66477 ,  H01L21/265 ,  H01L21/823418 ,  H01L21/823814 ,  H01L27/027 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/78612

    Abstract: A method for fabricating an ESD protection device . Agate electrode of a core device is formed in a non I/O region and a gate electrode of an ESD protection device is formed in a I/O region. A first photoresist film masks the I/O region and reveals the non I/O region. The first photoresist film includes at least an opening adjacent to the gate electrode of the ESD protection device in the I/O region. A core pocket implantation process using the first photoresist film as an implant mask is performed to implant dopants of a second conductivity type into the I/O region through the opening and into the non I/O region, thereby forming a core pocket doping region in the I/O region and core pocket doping regions in the non I/O region.

    Abstract translation: 一种制造ESD保护装置的方法。 核心器件的玛瑙电极形成在非I / O区域中，并且ESD保护器件的栅电极形成在I / O区域中。 第一光致抗蚀剂膜掩蔽I / O区域并显露非I / O区域。 第一光致抗蚀剂膜包括与I / O区域中的ESD保护装置的栅电极相邻的至少一个开口。 执行使用第一光致抗蚀剂膜作为注入掩模的核心袋注入工艺，以将第二导电类型的掺杂剂通过开口注入I / O区域并进入非I / O区域，由此形成核心袋掺杂区域 非I / O区域中的I / O区域和核心袋掺杂区域。

    HVMOS transistor structure having offset distance and method for fabricating the same
    7.
    发明授权
    HVMOS transistor structure having offset distance and method for fabricating the same 有权
    具有偏移距离的HVMOS晶体管结构及其制造方法

    公开(公告)号：US09231097B2

    公开(公告)日：2016-01-05

    申请号：US13760354

    申请日：2013-02-06

    Applicant: MediaTek Inc.

    Inventor： Ming-Cheng Lee

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/45 ,  H01L29/49 ,  H01L29/08

    CPC classification number: H01L29/78 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/41775 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66689

    Abstract: An HVMOS transistor structure includes: a first ion well of a first conductivity type and a second ion well of a second conductivity type different from the first conductivity type formed over a substrate, wherein the first ion well and the second ion well have a junction at their interface; a gate overlying the first ion well and the second ion well; a drain region of the first conductivity type, in the first ion well, spaced apart from a first sidewall of the gate by an offset distance; and a source region of the first conductivity type in the second ion well. In addition, a method for fabricating the HVMOS transistor structure described above is also provided.

    Abstract translation: HVMOS晶体管结构包括：第一导电类型的第一离子阱和不同于在衬底上形成的第一导电类型的第二导电类型的第二离子阱，其中第一离子阱和第二离子阱具有在 他们的界面 覆盖第一离子阱的栅极和第二离子阱; 所述第一导电类型的漏极区在所述第一离子阱中与所述栅极的第一侧壁间隔开偏移距离; 以及第二离子阱中的第一导电类型的源极区。 此外，还提供了一种用于制造上述HVMOS晶体管结构的方法。

    HIGH-VOLTAGE METAL-DIELECTRIC-SEMICONDUCTOR DEVICE AND METHOD OF THE SAME
    8.
    发明申请
    HIGH-VOLTAGE METAL-DIELECTRIC-SEMICONDUCTOR DEVICE AND METHOD OF THE SAME 审中-公开
    高压金属 - 介电半导体器件及其方法

    公开(公告)号：US20140103433A1

    公开(公告)日：2014-04-17

    申请号：US14140544

    申请日：2013-12-26

    Applicant: MEDIATEK INC.

    Inventor： Ming-Cheng Lee ,  Wei-Li Tsao

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423

    CPC classification number: H01L29/7835 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/42372 ,  H01L29/4983

    Abstract: A high-voltage metal-dielectric-semiconductor transistor includes a semiconductor substrate; a trench isolation region in the semiconductor substrate surrounding an active area; a gate overlying the active area; a drain doping region of a first conductivity type in the active area; a source doping region of the first conductivity type in a first well of a second conductivity type in the active area; and a source lightly doped region of the first conductivity type between the gate and the source doping region; wherein no isolation is formed between the gate and the drain doping region.

    Abstract translation: 高压金属电介质半导体晶体管包括半导体衬底; 围绕有源区的半导体衬底中的沟槽隔离区; 一个覆盖活跃区域的门; 在有源区中的第一导电类型的漏极掺杂区; 在有源区域中的第二导电类型的第一阱中的第一导电类型的源极掺杂区域; 以及在栅极和源极掺杂区域之间的第一导电类型的源极轻掺杂区域; 其中在栅极和漏极掺杂区域之间不形成隔离。

    Semiconductor devices and methods of forming the same
    10.
    发明授权
    Semiconductor devices and methods of forming the same 有权

    公开(公告)号：US11600700B2

    公开(公告)日：2023-03-07

    申请号：US17513819

    申请日：2021-10-28

    Applicant: MediaTek Inc.

    Inventor： Cheng-Tien Wan ,  Ming-Cheng Lee

    IPC: H01L21/8238 ,  H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor fin over a substrate, and a gate structure along sidewalls and the top surface of the semiconductor fin. The gate structure covers the first portion of the semiconductor fin. The semiconductor device also includes a source/drain feature adjacent to the gate structure. The semiconductor device further includes a source/drain contact connected to the source/drain feature. The source/drain contact extends downwards to a position that is lower than the top surface of the first portion of the semiconductor fin.

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