公开(公告)号：US09899261B2

公开(公告)日：2018-02-20

申请号：US15365394

申请日：2016-11-30

Applicant: MediaTek Inc.

Inventor： Cheng-Chou Hung ,  Ming-Tzong Yang ,  Tung-Hsing Lee ,  Wei-Che Huang ,  Yu-Hua Huang ,  Tzu-Hung Lin

IPC: H01L23/48 ,  H01L21/768 ,  H01L29/06 ,  H01L21/761 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/76898 ,  H01L21/761 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L29/0619 ,  H01L29/0623 ,  H01L2224/13 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package structure having a substrate, wherein the substrate has a front side and a back side, a through silicon via (TSV) interconnect structure formed in the substrate, and a first guard ring doped region and a second guard ring doped region formed in the substrate. The second guard ring doped region is disposed between the first guard ring doped region and the TSV interconnect structure.

公开(公告)号：US09620640B2

公开(公告)日：2017-04-11

申请号：US14450445

申请日：2014-08-04

Applicant: MediaTek Inc.

Inventor： Cheng-Chou Hung ,  Tung-Hsing Lee ,  Bernard Mark Tenbroek ,  Rong-Tang Chen

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/783 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/4975 ,  H01L29/78615 ,  H01L29/78654 ,  H01L29/78657

Abstract: The invention provides a body-contact metal-oxide-semiconductor field effect transistor (MOSFET) device. The body-contact MOSFET device includes a substrate. An active region is disposed on the substrate. A gate strip is extended along a first direction disposed on a first portion of the active region. A source doped region and a drain doped region are disposed on a second portion and a third portion of the active region, adjacent to opposite sides of the gate strip. The opposite sides of the gate strip are extended along the first direction. A body-contact doped region is disposed on a fourth portion of the active region. The body-contact doped region is separated from the gate strip by a fifth portion of the active region. The fifth portion is not covered by any silicide features.

公开(公告)号：US09947624B2

公开(公告)日：2018-04-17

申请号：US15393387

申请日：2016-12-29

Applicant: MediaTek Inc.

Inventor： Ming-Tzong Yang ,  Cheng-Chou Hung ,  Wei-Che Huang ,  Yu-Hua Huang ,  Tzu-Hung Lin ,  Kuei-Ti Chan ,  Ruey-Beei Wu ,  Kai-Bin Wu

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/5384 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/14 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2225/06541 ,  H01L2225/06544

Abstract: The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor package mounted on a base, having: a semiconductor die, a semiconductor substrate, and a first array of TSV interconnects and a second array of TSV interconnects formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. The assembly further includes a second semiconductor die mounted on the first semiconductor package, having a ground pad thereon. One of the TSV interconnects of the first semiconductor package has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.

公开(公告)号：US09640489B2

公开(公告)日：2017-05-02

申请号：US14320725

申请日：2014-07-01

Applicant: MediaTek Inc.

Inventor： Cheng-Chou Hung ,  Tung-Hsing Lee ,  Yu-Hua Huang ,  Ming-Tzong Yang

IPC: H01L21/02 ,  H01L23/00 ,  H01L23/58 ,  H01L29/94 ,  H01L27/08

CPC classification number: H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L27/0805 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type having a chip region enclosed by a seal ring region. An insulating layer is on the semiconductor substrate. A seal ring structure is embedded in the insulating layer corresponding to the seal ring region. And, a plurality of doping regions are located beneath the first seal ring structure.

公开(公告)号：US09607894B2

公开(公告)日：2017-03-28

申请号：US14621682

申请日：2015-02-13

Applicant: MediaTek Inc.

Inventor： Ming-Tzong Yang ,  Cheng-Chou Hung ,  Tung-Hsing Lee ,  Wei-Che Huang ,  Yu-Hua Huang

IPC: H01L23/66 ,  H01L23/12 ,  H01L25/04 ,  H01L21/768 ,  H01L23/522 ,  H01L31/18 ,  H01L23/48 ,  H01L23/00 ,  H01L21/02 ,  H01L21/268 ,  H01L21/306

CPC classification number: H01L21/76898 ,  H01L21/02107 ,  H01L21/268 ,  H01L21/30625 ,  H01L23/481 ,  H01L23/5227 ,  H01L23/66 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L31/18 ,  H01L2223/6616 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/11 ,  H01L2924/12042 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic device package has a base and an electronic device chip mounted on the base. The electronic device chip includes a semiconductor substrate having a front side and a back side, a electronic component disposed on the front side of the semiconductor substrate, an interconnect structure disposed on the electronic component, a through hole formed through the semiconductor substrate from the back side of the semiconductor substrate, connecting to the interconnect structure, and a TSV structure disposed in the through hole. The interconnect structure is electrically connected to the RF component, and a thickness of the semiconductor substrate is less than that of the interconnect structure.

公开(公告)号：US09570399B2

公开(公告)日：2017-02-14

申请号：US14963451

申请日：2015-12-09

Applicant: MediaTek Inc.

Inventor： Ming-Tzong Yang ,  Cheng-Chou Hung ,  Wei-Che Huang ,  Yu-Hua Huang ,  Tzu-Hung Lin ,  Kuei-Ti Chan ,  Ruey-Beei Wu ,  Kai-Bin Wu

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/5384 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/14 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2225/06541 ,  H01L2225/06544

Abstract: The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor die mounted on a base. The first semiconductor die includes a semiconductor substrate. A first array of TSV interconnects and a second array of TSV interconnects are formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. A first ground TSV interconnect is disposed within the interval region. A second semiconductor die is mounted on the first semiconductor die, having a ground pad thereon. The first ground TSV interconnect of the first semiconductor die has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.

Abstract translation: 本发明提供一种具有TSV互连的半导体封装组件。 半导体封装组件包括安装在基座上的第一半导体管芯。 第一半导体管芯包括半导体衬底。 通过半导体衬底形成TSV互连的第一阵列和TSV互连的第二阵列，其中TSV互连的第一阵列和第二阵列被间隔区隔开。 第一接地TSV互连设置在间隔区域内。 第二半导体管芯安装在第一半导体管芯上，其上具有接地焊盘。 第一半导体管芯的第一接地TSV互连具有耦合到第二半导体管芯的接地焊盘的第一端子和耦合到布置在半导体衬底的前侧上的互连结构的第二端子。

公开(公告)号：US09786560B2

公开(公告)日：2017-10-10

申请号：US15365435

申请日：2016-11-30

Applicant: MediaTek Inc.

Inventor： Cheng-Chou Hung ,  Ming-Tzong Yang ,  Tung-Hsing Lee ,  Wei-Che Huang ,  Yu-Hua Huang ,  Tzu-Hung Lin

IPC: H01L23/48 ,  H01L21/768 ,  H01L29/06 ,  H01L21/761 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/76898 ,  H01L21/761 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L29/0619 ,  H01L29/0623 ,  H01L2224/13 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor package structure is provided. The method for forming a semiconductor package structure includes providing a substrate, wherein the substrate has a front side and a back side, forming a first guard ring doped region and a second guard ring doped region in the substrate, wherein the first guard ring doped region and the second guard ring doped region have different conductive types, forming a trench through the substrate from a back side of the substrate, conformally forming an insulating layer lining the back side of the substrate, a bottom surface and sidewalls of the trench, removing a portion of the insulating layer on the back side of the substrate to form a through via, and forming a conductive material in the through via, wherein a through silicon via (TSV) interconnect structure is formed by the insulating layer and the conductive material.

公开(公告)号：US09543232B2

公开(公告)日：2017-01-10

申请号：US14601440

申请日：2015-01-21

Applicant: MediaTek Inc.

Inventor： Cheng-Chou Hung ,  Ming-Tzong Yang ,  Tung-Hsing Lee ,  Wei-Che Huang ,  Yu-Hua Huang ,  Tzu-Hung Lin

IPC: H01L23/48 ,  H01L29/06 ,  H01L21/761 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/761 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L29/0619 ,  H01L29/0623 ,  H01L2224/13 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package structure and method for forming the same are provided. The semiconductor package structure includes a substrate and the substrate has a front side and a back side. The semiconductor package structure includes a through silicon via (TSV) interconnect structure formed in the substrate; and a first guard ring doped region and a second guard ring doped region formed in the substrate, and the first guard ring doped region and the second guard ring doped region are adjacent to the TSV interconnect structure.

Abstract translation: 提供一种半导体封装结构及其形成方法。 半导体封装结构包括衬底，并且衬底具有正面和背面。 半导体封装结构包括在衬底中形成的穿硅通孔（TSV）互连结构; 以及形成在所述衬底中的第一保护环掺杂区域和第二保护环掺杂区域，并且所述第一保护环掺杂区域和所述第二保护环掺杂区域与所述TSV互连结构相邻。

公开(公告)号：US09425098B2

公开(公告)日：2016-08-23

申请号：US14621703

申请日：2015-02-13

Applicant: MediaTek Inc.

Inventor： Ming-Tzong Yang ,  Cheng-Chou Hung ,  Tung-Hsing Lee ,  Wei-Che Huang ,  Yu-Hua Huang

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/268 ,  H01L21/306 ,  H01L23/522 ,  H01L31/18 ,  H01L23/48 ,  H01L21/02 ,  H01L23/66

CPC classification number: H01L21/76898 ,  H01L21/02107 ,  H01L21/268 ,  H01L21/30625 ,  H01L23/481 ,  H01L23/5227 ,  H01L23/66 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L31/18 ,  H01L2223/6616 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/11 ,  H01L2924/12042 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for fabricating a electronic device package provides a electronic device chip, wherein the electronic device chip includes a semiconductor substrate having a front side and a back side, wherein the semiconductor substrate has a first thickness, an electronic component disposed on the front side of the semiconductor substrate, and an interconnect structure disposed on the electronic component. The method further performs a thinning process to remove a portion of the semiconductor substrate from the back side thereof. The method then removes a portion of the thinned semiconductor substrate and a portion of a dielectric layer of the interconnect structure from a back side of the thinned semiconductor substrate until a first metal layer pattern of the interconnect structure is exposed, thereby forming a through hole. Finally, the method forms a TSV structure in the through hole, and mounts the electronic device chip on a base.

Abstract translation: 一种制造电子器件封装的方法，提供了一种电子器件芯片，其中电子器件芯片包括具有正面和背面的半导体衬底，其中半导体衬底具有第一厚度，电子部件设置在第一厚度的前侧 半导体衬底和布置在电子部件上的互连结构。 该方法还进行薄膜化处理以从其背面去除半导体衬底的一部分。 然后，该方法从减薄的半导体衬底的背面去除一部分减薄的半导体衬底和互连结构的电介质层的一部分，直到互连结构的第一金属层图案被暴露，从而形成通孔。 最后，该方法在通孔中形成TSV结构，并将电子设备芯片安装在基座上。

公开(公告)号：US09269664B2

公开(公告)日：2016-02-23

申请号：US13846138

申请日：2013-03-18

Applicant: MediaTek Inc.

Inventor： Ming-Tzong Yang ,  Cheng-Chou Hung ,  Yu-Hua Huang ,  Wei-Che Huang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: The invention provides a semiconductor package with a through silicon via (TSV) interconnect and a method for fabricating the same. An exemplary embodiment of the semiconductor package with a TSV interconnect includes a semiconductor substrate. A through hole is formed through the semiconductor substrate. A TSV interconnect is disposed in a through hole. A conductive layer lines a sidewall of the through hole, surrounding the TSV interconnect.

Abstract translation: 本发明提供一种具有贯通硅通孔（TSV）互连的半导体封装及其制造方法。 具有TSV互连的半导体封装的示例性实施例包括半导体衬底。 通过半导体衬底形成通孔。 TSV互连设置在通孔中。 导电层将通孔的侧壁连接起来，围绕TSV互连。