公开(公告)号：US11715754B2

公开(公告)日：2023-08-01

申请号：US17319078

申请日：2021-05-12

Applicant: MEDIATEK INC.

Inventor： Zheng Zeng ,  Ching-Chung Ko ,  Kuei-Ti Chan

IPC: H01L23/48 ,  H01L49/02 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L28/10 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2225/06513 ,  H01L2924/1436 ,  H01L2924/182 ,  H01L2924/19042

Abstract: A semiconductor package includes a first die comprising an upper surface and a lower surface opposite to the upper surface. The first die includes a plurality of through-silicon vias (TSVs) penetrating through the first die. A second die is stacked on the upper surface of the first die. An interposer layer is disposed on the lower surface of the first die. An inductor is disposed in the interposer layer. The inductor comprises terminals directly coupled to the TSVs.

公开(公告)号：US20210384291A1

公开(公告)日：2021-12-09

申请号：US17319078

申请日：2021-05-12

Applicant: MEDIATEK INC.

Inventor： Zheng Zeng ,  Ching-Chung Ko ,  Kuei-Ti Chan

IPC: H01L49/02 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor package includes a first die comprising an upper surface and a lower surface opposite to the upper surface. The first die includes a plurality of through-silicon vias (TSVs) penetrating through the first die. A second die is stacked on the upper surface of the first die. An interposer layer is disposed on the lower surface of the first die. An inductor is disposed in the interposer layer. The inductor comprises terminals directly coupled to the TSVs.

公开(公告)号：US12142633B2

公开(公告)日：2024-11-12

申请号：US18332863

申请日：2023-06-12

Applicant: MediaTek Inc.

Inventor： Zheng Zeng ,  Ching-Chung Ko ,  Kuei-Ti Chan

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L49/02

Abstract: A semiconductor package includes a first die comprising an upper surface and a lower surface opposite to the upper surface. The first die includes a plurality of through-silicon vias (TSVs) penetrating through the first die. A second die is stacked on the upper surface of the first die. An interposer layer is disposed on the lower surface of the first die. An inductor is disposed in the interposer layer. The inductor comprises terminals directly coupled to the TSVs.

公开(公告)号：US09947624B2

公开(公告)日：2018-04-17

申请号：US15393387

申请日：2016-12-29

Applicant: MediaTek Inc.

Inventor： Ming-Tzong Yang ,  Cheng-Chou Hung ,  Wei-Che Huang ,  Yu-Hua Huang ,  Tzu-Hung Lin ,  Kuei-Ti Chan ,  Ruey-Beei Wu ,  Kai-Bin Wu

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/5384 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/14 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2225/06541 ,  H01L2225/06544

Abstract: The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor package mounted on a base, having: a semiconductor die, a semiconductor substrate, and a first array of TSV interconnects and a second array of TSV interconnects formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. The assembly further includes a second semiconductor die mounted on the first semiconductor package, having a ground pad thereon. One of the TSV interconnects of the first semiconductor package has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.

公开(公告)号：US09570399B2

公开(公告)日：2017-02-14

申请号：US14963451

申请日：2015-12-09

Applicant: MediaTek Inc.

Inventor： Ming-Tzong Yang ,  Cheng-Chou Hung ,  Wei-Che Huang ,  Yu-Hua Huang ,  Tzu-Hung Lin ,  Kuei-Ti Chan ,  Ruey-Beei Wu ,  Kai-Bin Wu

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/5384 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/14 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2225/06541 ,  H01L2225/06544

Abstract: The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor die mounted on a base. The first semiconductor die includes a semiconductor substrate. A first array of TSV interconnects and a second array of TSV interconnects are formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. A first ground TSV interconnect is disposed within the interval region. A second semiconductor die is mounted on the first semiconductor die, having a ground pad thereon. The first ground TSV interconnect of the first semiconductor die has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.

Abstract translation: 本发明提供一种具有TSV互连的半导体封装组件。 半导体封装组件包括安装在基座上的第一半导体管芯。 第一半导体管芯包括半导体衬底。 通过半导体衬底形成TSV互连的第一阵列和TSV互连的第二阵列，其中TSV互连的第一阵列和第二阵列被间隔区隔开。 第一接地TSV互连设置在间隔区域内。 第二半导体管芯安装在第一半导体管芯上，其上具有接地焊盘。 第一半导体管芯的第一接地TSV互连具有耦合到第二半导体管芯的接地焊盘的第一端子和耦合到布置在半导体衬底的前侧上的互连结构的第二端子。

公开(公告)号：US09548271B2

公开(公告)日：2017-01-17

申请号：US14932122

申请日：2015-11-04

Applicant: MediaTek Inc

Inventor： Kuei-Ti Chan ,  Tzu-Hung Lin ,  Ching-Liou Huang

IPC: H01L29/40 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01Q23/00 ,  H01L23/31 ,  H01L23/64 ,  H01L23/66 ,  H01L23/525

CPC classification number: H01L23/528 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/645 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2223/6677 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/12 ,  H01L2924/1206 ,  H01Q23/00 ,  H01L2224/05552

Abstract: A semiconductor package includes a substrate, a first passivation layer disposed on the substrate, and an under bump metallurgy layer disposed on the first passivation layer. An additional under bump metallurgy layer is disposed on the first passivation layer, isolated from the under bump metallurgy layer; and a conductive pillar disposed on the additional under bump metallurgy layer.

Abstract translation: 半导体封装包括衬底，设置在衬底上的第一钝化层和设置在第一钝化层上的凸块下金属层。 附加的凸块下冶金层设置在与凸块下金属层隔离的第一钝化层上; 以及设置在附加的凸块下金属层上的导电柱。

公开(公告)号：US09209148B2

公开(公告)日：2015-12-08

申请号：US14663755

申请日：2015-03-20

Applicant: MediaTek Inc

Inventor： Kuei-Ti Chan ,  Tzu-Hung Lin ,  Ching-Liou Huang

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/522 ,  H01Q23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L23/64 ,  H01L23/66 ,  H01L23/525

CPC classification number: H01L23/528 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/645 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2223/6677 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/12 ,  H01L2924/1206 ,  H01Q23/00 ,  H01L2224/05552

Abstract: A semiconductor package includes a substrate, a first passivation layer disposed on the substrate, and an under bump metallurgy layer disposed on the first passivation layer. A passive device is disposed on the under bump metallurgy layer, and an additional under bump metallurgy layer is disposed on the first passivation layer, isolated from the under bump metallurgy layer. A conductive pillar is disposed on the additional under bump metallurgy layer, wherein the conductive pillar and the passive device are at the same level.

Abstract translation: 半导体封装包括衬底，设置在衬底上的第一钝化层和设置在第一钝化层上的凸块下金属层。 无源器件设置在凸块下金属层上，并且附加的凸块下金属层设置在与凸块下金属层隔离的第一钝化层上。 导电柱设置在另外的凸块下金属层上，其中导电柱和无源器件处于同一水平。

公开(公告)号：US20240079444A1

公开(公告)日：2024-03-07

申请号：US18332863

申请日：2023-06-12

Applicant: MediaTek Inc.

Inventor： Zheng Zeng ,  Ching-Chung Ko ,  Kuei-Ti Chan

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L28/10 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2225/06513 ,  H01L2924/1436 ,  H01L2924/182 ,  H01L2924/19042

Abstract: A semiconductor package includes a first die comprising an upper surface and a lower surface opposite to the upper surface. The first die includes a plurality of through-silicon vias (TSVs) penetrating through the first die. A second die is stacked on the upper surface of the first die. An interposer layer is disposed on the lower surface of the first die. An inductor is disposed in the interposer layer. The inductor comprises terminals directly coupled to the TSVs.