公开(公告)号：US20130250661A1

公开(公告)日：2013-09-26

申请号：US13427339

申请日：2012-03-22

Applicant: Gurtej S. Sandhu ,  Wayne I. Kinney

Inventor： Gurtej S. Sandhu ,  Wayne I. Kinney

IPC: G11C11/16 ,  H01L29/82 ,  H01L21/8246

CPC classification number: H01L43/08 ,  G11C11/15 ,  G11C11/161 ,  H01F10/1936 ,  H01F10/3286 ,  H01F10/329 ,  H01L27/228 ,  H01L43/02 ,  H01L43/12

Abstract: Memory cells including cell cores having free regions are disclosed. The free regions exhibit a strain that affects a magnetization orientation within the cell core. A stressor structure may exert a stress upon at least a portion of the cell core to effect the strain state of the free region. Also disclosed are semiconductor device structures and systems including such memory cells as well as methods for forming such memory cells.

Abstract translation: 公开了包括具有自由区域的单元芯的存储单元。 自由区域表现出影响细胞核心内的磁化取向的应变。 应力结构可能对细胞芯的至少一部分施加应力以实现自由区的应变状态。 还公开了包括这种存储单元的半导体器件结构和系统以及用于形成这种存储单元的方法。

公开(公告)号：US4649627A

公开(公告)日：1987-03-17

申请号：US625758

申请日：1984-06-28

Applicant: John R. Abernathey ,  Wayne I. Kinney ,  Jerome B. Lasky ,  Scott R. Stiffler

Inventor： John R. Abernathey ,  Wayne I. Kinney ,  Jerome B. Lasky ,  Scott R. Stiffler

IPC: H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/00 ,  H01L27/06 ,  H01L27/092 ,  H01L27/12 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78

CPC classification number: H01L27/0688 ,  H01L21/2007 ,  H01L21/76251 ,  H01L21/8221 ,  Y10S148/135 ,  Y10S148/15 ,  Y10S148/164

Abstract: A method of fabricating a shared element semiconductor structure in which the insulating layer of a silicon-on-insulator structure is patterned to form a gate oxide. The bulk semiconductor underlying the insulating layer is defined into an FET (field-effect transistor) with its gate region below the gate oxide. The epitaxial layer above the insulating layer is defined into another FET with its drain region above the gate oxide, whereby the drain region also operates as the gate electrode for the bulk FET. Also described is a method of forming a silicon on insulator substrate with insulating layer usable as a gate oxide by means of bonding a silicon substrate to an oxidized epitaxial layer on another silicon seed substrate and then removing the seed substrate.

Abstract translation: 一种制造共模元件半导体结构的方法，其中将绝缘体上硅结构的绝缘层图案化以形成栅极氧化物。 绝缘层下面的体半导体被定义为FET（场效应晶体管），其栅极区在栅极氧化物的下面。 绝缘层之上的外延层被定义为另一个FET，其漏极区在栅极氧化物的上方，由此漏区也作为体FET的栅极工作。 还描述了一种通过将硅衬底粘合到另一个硅种子衬底上的氧化外延层，然后去除种子衬底，形成具有可用作栅极氧化物的绝缘层的绝缘体上硅衬底的方法。

公开(公告)号：US20140070342A1

公开(公告)日：2014-03-13

申请号：US13614212

申请日：2012-09-13

Applicant: Gurtej S. Sandhu ,  Witold Kula ,  Wayne I. Kinney

Inventor： Gurtej S. Sandhu ,  Witold Kula ,  Wayne I. Kinney

IPC: H01L43/12 ,  H01L29/82

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L27/224 ,  H01L27/226 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Methods of forming memory cells, magnetic memory cell structures, and arrays of magnetic memory cell structures are disclosed. Embodiments of the methods include patterning a precursor structure to form a stepped structure including at least an upper discrete feature section and a lower feature section with a broader width, length, or both than the upper discrete feature section. The method uses patterning acts directed along a first axis, e.g., an x-axis, and then along a second axis, e.g., a y-axis, that is perpendicular to or about perpendicular to the first axis. The patterning acts may therefore allow for more unifoimity between a plurality of formed, neighboring cell core structures, even at dimensions below about thirty nanometers. Magnetic memory structures and memory cell arrays are also disclosed.

Abstract translation: 公开了形成存储单元，磁存储单元结构和磁存储单元结构阵列的方法。 方法的实施例包括图案化前体结构以形成包括至少上部离散特征部分和具有更宽的宽度，长度或两者比较高离散特征部分的下部特征部分的阶梯式结构。 该方法使用沿着第一轴线例如x轴，然后沿着垂直于第一轴线或垂直于第一轴线的第二轴线，例如y轴定向的图案化动作。 因此，即使在低于约三十纳米的尺寸下，图案化动作也可允许在多个形成的相邻电池芯结构之间的更大的均匀性。 还公开了磁存储器结构和存储单元阵列。

公开(公告)号：US20130334631A1

公开(公告)日：2013-12-19

申请号：US13527262

申请日：2012-06-19

Applicant: Wayne I. Kinney ,  Witold Kula ,  Stephen J. Kramer

Inventor： Wayne I. Kinney ,  Witold Kula ,  Stephen J. Kramer

IPC: H01L29/82 ,  G11B5/673 ,  G11B5/65 ,  H01L21/34 ,  G11B5/66

CPC classification number: H01L27/222 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01F10/3218 ,  H01F10/329 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Memory cells are disclosed. Magnetic regions within the memory cells include an alternating structure of magnetic sub-regions and coupler sub-regions. The coupler material of the coupler sub-regions antiferromagnetically couples neighboring magnetic sub-regions and effects or encourages a vertical magnetic orientation exhibited by the neighboring magnetic sub-regions. Neighboring magnetic sub-regions, spaced from one another by a coupler sub-region, exhibit oppositely-directed magnetic orientations. The magnetic and coupler sub-regions may each be of a thickness tailored to form the magnetic region in a compact structure. Interference between magnetic dipole fields emitted from the magnetic region on switching of a free region in the memory cell may be reduced or eliminated. Also disclosed are semiconductor device structures, spin torque transfer magnetic random access memory (STT-MRAM) systems, and methods of fabrication.

Abstract translation: 公开了存储单元。 存储单元内的磁性区域包括磁性子区域和耦合器子区域的交替结构。 耦合器子区域的耦合器材料反铁磁耦合相邻磁性子区域并且影响或促进相邻磁性子区域呈现的垂直磁性取向。 通过耦合器子区彼此间隔开的相邻的磁子区域表现出相反方向的磁取向。 磁性和耦合器子区域可以各自具有被调整以在紧凑结构中形成磁性区域的厚度。 可以减少或消除在切换存储单元中的自由区域时从磁性区域发射的磁偶极子场之间的干扰。 还公开了半导体器件结构，自旋扭矩传递磁随机存取存储器（STT-MRAM）系统和制造方法。

公开(公告)号：US5541872A

公开(公告)日：1996-07-30

申请号：US450916

申请日：1995-05-26

Applicant: Tyler A. Lowrey ,  Wayne I. Kinney

Inventor： Tyler A. Lowrey ,  Wayne I. Kinney

IPC: G11C11/22

CPC classification number: G11C11/22

Abstract: Described herein is a reference voltage circuit which includes, in combination, a bit line and first and second word line reference transistors connected to the bit line and operative to be turned on with a reference pulse simultaneously with the turning on of the word lines in the main memory circuit. First and second ferroelectric capacitors are connected to each of the first and second word line reference transistors, respectively, and to a source of plate line switching voltage, and a first precharging transistor is connected between the first ferroelectric capacitor and ground potential. A second precharging transistor is connected between the second ferroelectric capacitor and a further source of switching voltage, so that the first and second ferroelectric capacitors are polarized in a ONE and ZERO state in the manner identical to the logic states of the ferroelectric capacitors in the main ferroelectric memory circuit. Thus, when the first and second word line reference transistors turn on, the bit line reference voltage is raised above ground potential by the sum of the voltages of the first and second ferroelectric capacitors. This in turn causes the bit line reference voltage, BL, to track the voltage variations of the ferroelectric capacitors in the main memory circuit, thus providing improved margins for the BL and BL complementary signals which are sensed by a plurality of sense amplifiers for the main memory circuit.

Abstract translation: 这里描述了一种参考电压电路，其组合包括连接到位线的位线和第一和第二字线参考晶体管，并且可操作地与基准脉冲导通，同时在 主存电路。 第一和第二铁电电容器分别连接到第一和第二字线参考晶体管中的每一个以及板线切换电压源，并且第一预充电晶体管连接在第一铁电电容器和地电位之间。 第二预充电晶体管连接在第二铁电电容器和另一开关电压源之间，使得第一和第二铁电电容器以与主电容器中的铁电电容器的逻辑状态相同的方式以一个和第零个状态极化 铁电存储电路。 因此，当第一和第二字线参考晶体管导通时，位线参考电压通过第一和第二铁电电容器的电压之和而升高到地电位以上。 这又导致位线参考电压+ E，ovs BL + EE跟踪主存储器电路中的铁电电容器的电压变化，从而为BL和+ E，ovs BL + EE互补信号提供改善的余量 其由用于主存储器电路的多个读出放大器感测。

公开(公告)号：US5424975A

公开(公告)日：1995-06-13

申请号：US175923

申请日：1993-12-30

Applicant: Tyler A. Lowrey ,  Wayne I. Kinney

Inventor： Tyler A. Lowrey ,  Wayne I. Kinney

IPC: G11C11/22

CPC classification number: G11C11/22

Abstract: Described herein is a reference voltage circuit which includes, in combination, a bit line and first and second word line reference transistors connected to the bit line and operative to be turned on with a reference pulse simultaneously with the turning on of the word lines in the main memory circuit. First and second ferroelectric capacitors are connected to each of the first and second word line reference transistors, respectively, and to a source of plate line switching voltage, and a first precharging transistor is connected between the first ferroelectric capacitor and ground potential. A second precharging transistor is connected between the second ferroelectric capacitor and a further source of switching voltage, so that the first and second ferroelectric capacitors are polarized in a ONE and ZERO state in the manner identical to the logic states of the ferroelectric capacitors in the main ferroelectric memory circuit. Thus, when the first and second word line reference transistors turn on, the bit line reference voltage is raised above ground potential by the sum of the voltages of the first and second ferroelectric capacitors. This in turn causes the bit line reference voltage, BL, to track the voltage variations of the ferroelectric capacitors in the main memory circuit, thus providing improved margins for the BL and BL complementary signals which are sensed by a plurality of sense amplifiers for the main memory circuit.

Abstract translation: 这里描述了一种参考电压电路，其组合包括连接到位线的位线和第一和第二字线参考晶体管，并且可操作地与基准脉冲导通，同时在 主存电路。 第一和第二铁电电容器分别连接到第一和第二字线参考晶体管中的每一个以及板线切换电压源，并且第一预充电晶体管连接在第一铁电电容器和地电位之间。 第二预充电晶体管连接在第二铁电电容器和另一开关电压源之间，使得第一和第二铁电电容器以与主电容器中的铁电电容器的逻辑状态相同的方式以一个和第零个状态极化 铁电存储电路。 因此，当第一和第二字线参考晶体管导通时，位线参考电压通过第一和第二铁电电容器的电压之和而升高到地电位以上。 这又导致位线参考电压＆upbar＆B跟踪主存储器电路中的铁电电容器的电压变化，从而为由多个读出放大器感测的BL和＆amp; B和B互补信号提供改进的余量， 主存储电路。

公开(公告)号：US5179038A

公开(公告)日：1993-01-12

申请号：US456029

申请日：1989-12-22

Applicant: Wayne I. Kinney ,  John P. Niemi ,  Jonathan E. Macro ,  David Back

Inventor： Wayne I. Kinney ,  John P. Niemi ,  Jonathan E. Macro ,  David Back

IPC: H01L21/763 ,  H01L21/8238

CPC classification number: H01L21/823878 ,  H01L21/763 ,  Y10S438/911

Abstract: A method of forming isolation trenches in CMOS integrated circuits is disclosed. The trench side walls are covered by a thin oxide layer, and the trenches are filled with a highly doped polysilicon. The doped polysilicon has a high work function which prevents oxide charges from inverting the trench side walls and thereby turns off the parasitic transistors at these side walls to reduce latchup.

Abstract translation: 公开了一种在CMOS集成电路中形成隔离沟槽的方法。 沟槽侧壁被薄的氧化物层覆盖，并且沟槽填充有高度掺杂的多晶硅。 掺杂多晶硅具有高功函数，其防止氧化物电荷反转沟槽侧壁，从而在这些侧壁处关闭寄生晶体管以减少闭锁。

公开(公告)号：US4558508A

公开(公告)日：1985-12-17

申请号：US660673

申请日：1984-10-15

Applicant: Wayne I. Kinney ,  Charles W. Koburger, III ,  Jerome B. Lasky ,  Larry A. Nesbit ,  Ronald R. Troutman ,  Francis R. White

Inventor： Wayne I. Kinney ,  Charles W. Koburger, III ,  Jerome B. Lasky ,  Larry A. Nesbit ,  Ronald R. Troutman ,  Francis R. White

IPC: H01L27/08 ,  H01L21/033 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L21/22 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L21/76218 ,  H01L21/033 ,  H01L21/823892 ,  H01L29/0638 ,  H01L27/0928 ,  Y10S148/043 ,  Y10S148/053 ,  Y10S148/10 ,  Y10S148/157

Abstract: A process for making a CMOS dual-well semiconductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells to each other and also of the field isolation doping regions to the wells. The lithographic masking step forms a well mask and defines an oxidation barrier which acts as: an implant mask (absorber) during the ion-implantation of a field dopant of one type; an oxidation barrier over one well during the oxidation of the opposite-type well to form over the one well a sacrificial oxide layer which forms the alignment marks for subsequent formation of the field-doping regions; and a dopant-transmitter during the ion-implantation of an opposite-type field dopant which is simultaneously absorbed by the sacrificial oxide. As a result, there are formed field-doped oxide layers self-aligned to the wells so that, with a subsequent masking step, oxide field isolations are defined over the doped oxide layers. A heat cycle is then used to drive the field dopants into the corresponding field-doping regions.

Abstract translation: 制造具有场隔离掺杂的CMOS双阱半导体结构的方法，其中仅需要单个光刻掩模步骤，以提供阱彼此之间的自对准以及对阱的场隔离掺杂区域的自对准。 光刻掩模步骤形成了良好的掩模，并且限定了一种氧化屏障，其作用为在一种类型的场掺杂剂的离子注入期间的注入掩模（吸收体） 在相对孔的氧化期间在一个阱上形成氧化屏障，以在一个阱上形成牺牲氧化物层，其形成用于随后形成场掺杂区域的对准标记; 以及在由牺牲氧化物同时吸收的相反型场掺杂剂的离子注入期间的掺杂剂发射器。 结果，形成了与阱自对准的场掺杂氧化物层，使得通过随后的掩模步骤，在掺杂的氧化物层上限定氧化物场隔离。 然后使用热循环将场掺杂剂驱动到相应的场掺杂区域中。