Invention Grant
- Patent Title: High density trench isolation for MOS circuits
- Patent Title (中): MOS电路的高密度沟槽隔离
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Application No.: US456029Application Date: 1989-12-22
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Publication No.: US5179038APublication Date: 1993-01-12
- Inventor: Wayne I. Kinney , John P. Niemi , Jonathan E. Macro , David Back
- Applicant: Wayne I. Kinney , John P. Niemi , Jonathan E. Macro , David Back
- Applicant Address: CA Sunnyvale
- Assignee: North American Philips Corp., Signetics Division
- Current Assignee: North American Philips Corp., Signetics Division
- Current Assignee Address: CA Sunnyvale
- Main IPC: H01L21/763
- IPC: H01L21/763 ; H01L21/8238
Abstract:
A method of forming isolation trenches in CMOS integrated circuits is disclosed. The trench side walls are covered by a thin oxide layer, and the trenches are filled with a highly doped polysilicon. The doped polysilicon has a high work function which prevents oxide charges from inverting the trench side walls and thereby turns off the parasitic transistors at these side walls to reduce latchup.
Public/Granted literature
- US5776433A Flunisolide aerosol formulations Public/Granted day:1998-07-07
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