公开(公告)号：US5179038A

公开(公告)日：1993-01-12

申请号：US456029

申请日：1989-12-22

Applicant: Wayne I. Kinney ,  John P. Niemi ,  Jonathan E. Macro ,  David Back

Inventor： Wayne I. Kinney ,  John P. Niemi ,  Jonathan E. Macro ,  David Back

IPC: H01L21/763 ,  H01L21/8238

CPC classification number: H01L21/823878 ,  H01L21/763 ,  Y10S438/911

Abstract: A method of forming isolation trenches in CMOS integrated circuits is disclosed. The trench side walls are covered by a thin oxide layer, and the trenches are filled with a highly doped polysilicon. The doped polysilicon has a high work function which prevents oxide charges from inverting the trench side walls and thereby turns off the parasitic transistors at these side walls to reduce latchup.

Abstract translation: 公开了一种在CMOS集成电路中形成隔离沟槽的方法。 沟槽侧壁被薄的氧化物层覆盖，并且沟槽填充有高度掺杂的多晶硅。 掺杂多晶硅具有高功函数，其防止氧化物电荷反转沟槽侧壁，从而在这些侧壁处关闭寄生晶体管以减少闭锁。